Dipjyoti Das

We present an experimental study optimizing a band-engineered gate-stack by incorporating both a tunnel dielectric layer (TDL) and a gate blocking layer (GBL) for ferroelectric (FE) NAND flash applications, with a total thickness budget of 18 nm. Using Hf $_{\text{0}.\text{5}}$ Zr $_{\text{0}.\text{5}}$ O $_\text{2}$ (HZO) as the FE material, we explore Al $_\text{2}$ O $_\text{3}$ , SiO $_\text{2}$ , Si $_\text{3}$ N $_\text{4}$ , and HfO $_\text{2}$ as TDL and GBL materials. By systematically varying the location and thickness of each layer, we investigate their impact on memory window (MW) performance. Our results show that material choice and positioning within the gate-stack are critical, even with constant overall thickness. A hybrid stack using 2-nm Al $_\text{2}$ O $_\text{3}$ and 4-nm SiO $_\text{2}$ as TDL and GBL, respectively, results in a maximum MW of 11 V. When Al $_\text{2}$ O $_\text{3}$ and SiO $_\text{2}$ are positioned as GBL above the HZO layer, the MW is slightly reduced ( $>$ 7.5 V), with an increased tetragonal phase. Conversely, MW is significantly reduced when Al $_\text{2}$ O $_\text{3}$ and SiO $_\text{2}$ are used as GBL and TDL, respectively, or when both are used as TDL. Further exploration using SiO $_\text{2}$ , Si $_\text{3}$ N $_\text{4}$ , and HfO $_\text{2}$ as TDL materials with an SiO $_\text{2}$ GBL shows that HfO $_\text{2}$ and SiO $_\text{2}$ as TDL lead to quad-level cell (QLC)-compatible MW, whereas Si $_\text{3}$ N $_\text{4}$ as TDL leads to very low MW. HfO $_\text{2}$ as TDL material leads to most optimized gate-stack with QLC compatibility and lowest operating voltage of all materials. This study underscores the importance of dielectric (DE) material selection and layer positioning within the gate-stack in optimizing the MW of hybrid gate-stacks.

We study the disturb characteristics of ferroelectric field-effect transistors (FEFETs) with band-engineered gate stacks. We demonstrate that integrating a dielectric Al ₂ O ₃ layer within the ferroelectric (FE) Hf _0.5 Zr _0.5 O ₂ layer in the gate stack significantly enhances the memory window (MW), achieving levels suitable for quad-level cell operation (approximately 7.5 V) while operating at a reduced write voltage (below 15 V). Despite these improvements, the band-engineered FEFET exhibits similar pass disturb characteristics in the PGM state as a standard FEFET with an FE-only gate stack. To improve the disturb characteristics, we introduce and validate a periodic refresh-based disturb mitigation scheme, analogous to strategies employed in SSD controllers and flash memory managers for traditional charge trap flash-based NAND chips. This mitigation scheme reduces disturb in the PGM state from ~28% to approximately ~4% in the band-engineered FEFETs, enabling large memory window, lowdisturb operation.

We present an experimental study to compare the impacts of different dielectric materials - Al ₂ O ₃ and SiO ₂ used as the tunnel dielectric layer (TDL) and the gate blocking layer (GBL) on the performance of ferroelectric gate stacks for NAND storage applications. We considered the maximum memory window (MW) and the incremental step program pulse (ISPP) slope as the key performance metrics. In a gate stack with TDL, Al ₂ O ₃ gives higher MW and ISPP performance than SiO ₂ . However, in the GBL gate stack, SiO ₂ has a higher MW and ISPP slope than Al ₂ O ₃ . With SiO ₂ GBL, a maximum MW window of 8.3V was achieved, enabling quad-level cell (QLC) capability. We show that for a similar thickness, SiO ₂ as GBL has the better MW performance, and Al ₂ O ₃ as TDL has a better ISPP performance. This study shows that TDL and GBL with appropriate dielectric material can be used as tuning knobs to achieve the desired ISPP and MW performance for ferroelectric NAND applications.

A comprehensive quantitative root cause study of defect evolution leading to memory window closure from a charge balance and charge trapping perspective throughout all phases of a Si channel Hf0.5Zr0.5O2 (HZO) ferroelectric field-effect-transistor (FEFET) is reported. Starting with the first write pulse, an excessive SiO2 interlayer field is revealed that triggers the creation of defect levels Dit in excess of 1015 cm−2 eV−1 at the HZO–SiO2 interface screening ferroelectric (FE) polarization while enabling FE switching. Under subsequent early bipolar fatigue cycling (up to 104 cycles), defect creation commences at the SiO2–Si interface due to the high injected hole fluence (0.39 C/m2) during each stress pulse causing negative bias instability (NBI), which shifts the threshold voltage of the erase state VT,ERS by −0.3 V with accrual of permanently captured charge Nit of up to +5 × 10−3 C/m2 (3 × 1012 cm−2). Subsequently, Nit NBI generation at the SiO2–Si interface accelerates reaching levels of +7 × 10−2 C/m2, locking both FEFET program and erase drain current vs gate–source-voltage (ID–VGS) characteristics in the FEFET on-state inducing memory window closure at 105 cycles while FE switching (switched polarization Psw = 0.34 C/m2) remains essentially intact. These findings guide the down-selection toward suitable semiconductor/FE systems for charge balanced, reliable, and high endurance FEFETs.

Strategies to reduce the interfacial oxide layer thickness in ferroelectric (FE) Hf $_{\text{0}.\text{5}}$ Zr $_{\text{0}.\text{5}}$ O $_{\text{2}}$ (HZO) metal-oxide-semiconductor capacitor (FE-MOS) structures on Ge and Si substrates were investigated by electrode engineering, as means to reduce the write voltage in FE field-effect transistors (FEFETs). When the gate metal in Ge FE-MOS capacitors is changed from W (control) to Pt/Ti, the coercive voltage is reduced from $\sim$ 2.5 to $\sim$ 0.9 V (a 66% reduction) along with a 64% increase in the capacitance consistent with an interfacial layer (IL) thinning. High-resolution scanning transmission electron microscopy (HR-STEM) reveals no visible IL with Pt/Ti electrodes in Ge FE-MOS, suggesting the scavenging of oxygen from the GeO $_{\textit{x}}$ IL by the Pt/Ti electrode. However, a much smaller reduction of the coercive voltage was observed on Si FE-MOS structures with Pt/Ti electrodes. In this study, it is demonstrated that IL thinning might provide a pathway to reduce the write voltage in FEFETs based on conventional semiconductor channel materials down to a logic-compatible level.

A major roadblock for the integration of ferroelectric-field-effect transistors (FEFETs) at advanced technology nodes for embedded memory applications is their high, logic-incompatible write voltages. Herein, we explore Ge as a channel material to reduce write voltage of FEFET and report the first demonstration of p-type Ge-FEFETs with record low write voltages of ±1.4 V with a memory window (MW) of 0.6 V at DC and write voltages of ±1.4 V, ±1.8 V and ±2.4 V for MW of 0.2 V, 0.5 V and 0.8 V for a write time of 10 $\mu \text{s}$ , respectively. The write voltages observed in Ge-pFEFETs are ~50% lower than that of a Si-pFEFETs when compared against iso-memory window condition [±2.5 V with a MW of 0.6 V at DC, ±3.5 V for MW of 0.5 V for a write time of 10 $\mu \text{s}$ ]. Such dramatic reduction of write voltages in Ge-pFEFETs is achieved due to the fact that the native oxide of Ge (GeOx), formed at the Ge interface, has a larger dielectric constant and lower thickness than those for SiO2 on the Si platform. In addition, the lower bandgap and higher dielectric constant of Ge may lead to a lower surface potential for a given semiconductor charge, leading to further reduction in the write voltage. Further, our Ge-pFEFETs show write endurance of 107 cycles (the best-in-class for Ge-pFEFETs, as reported in the literature), excellent data retention, and immediate read-after-write capability. Our results indicate the attractiveness of Ge platform for FEFETs for embedded memory applications.

A Ferroelectric Field-Effect Transistor (FEFET) is a promising candidate for next-generation memory devices because it offers numerous advantages, such as its high speed, low energy profile, and nondestructive readout process. FEFETs merge logic and memory functionality in a single device, allowing efficient data transfer and a high packing density, which could make them vital for use in future in-memory computing architectures. Although issues related to the integration of perovskite materials in the state-of-the art semiconductor industry limited their commercial success, the discovery of ferroelectricity in CMOS-compatible doped hafnium oxides led to a re-emergence of FEFETs in advanced microelectronics. The demonstration of ferroelectricity in doped hafnia at extremely thin film thicknesses plus its low permittivity, high coercive field (Ec), environment-friendly composition, and excellent CMOS compatibility are expected to unleash the promise of FEFETs, and significant progress has been made in this regard.

The use of additional dielectric (DE) layers such as Al ₂ O ₃ , ZrO ₂ , HfO ₂ and Ta ₂ O ₅ with Hf _0.5 Zr _0.5 O ₂ (HZO) ferroelectric (FE) layer, namely bi-layer systems are drawing much attention in the recent past due to enhanced FE properties and their applications in memory technology. However, HZO based tri-layer capacitors with various DE layers are not yet reported. The present paper demonstrates the enhanced FE properties of MFM tri- layer capacitors were found at low temperature (350 °C) using rapid thermal annealing (RTA) process. Various tri-layer capacitors were fabricated by changing top dielectric layers such as TiO ₂ , ZrO ₂ and SiO ₂ (thickness of 10Å) while keeping FE HZO (100Å) and bottom HfO ₂ DE layer (10Å) as constant and traditional P-E curves for all those tri-layer (DE/FE/DE) capacitors were observed. Among all the tri-layer capacitors, highest remanent polarization ( P _r ~ 16.6 μC/cm ² ) was observed for the TiO ₂ top DE at 350 °C. The addition of top DE layers induced strain in the FE film due to their different thermal expansion coefficients and as a resulting in enhancing o-phase. The demonstration of excellent ferroelectric property by the as fabricated metal-ferroelectric-metal (MFM) capacitors with crystallization temperature as low as 350 °C can be of significant importance in sensor and display applications.

In this study, we have carried out an in-depth analysis on the role of high-pressure annealing (HPA) conditions on ferroelectricity as well as the interfacial property of Hf _x Zr _1-x O ₂ (HZO) capacitors in metal-ferroelectric-metal (MFM) structure. Unlike conventional 1:1 HZO films, HZO demonstrates the highest ferroelectricity at 1:3 Hf:Zr ratio in HPA and a significantly higher maximum remanent polarization ( P _r ) of 31 μC/cm ² was achieved as compared to 19 μC/cm ² obtained in rapid thermal annealing (RTA) (HZO [1:1]). To understand the influence of HPA conditions, HZO [1:3] capacitors are annealed at various temperatures (300 °C, 400 °C, 500 °C, and 600 °C) and pressures (1, 50, and 200 atm). Ferroelectricity in HZO is found to enhance with increasing HPA temperature or pressure due to higher ferroelectric phase formation as revealed by grazing incidence X-ray diffractometer (GIXRD) analysis. Transient pulse switching measurement suggests the reduction in the effective thickness of the interfacial nonferroelectric film at a high HPA temperature or pressure which was also validated by impedance analysis. Further, impedance analysis reveals a reduction in the number of oxygen vacancy defects with increasing annealing temperature or pressure implying a phase transition from the tetragonal phase of nonferroelectric layer to the ferroelectric orthorhombic phase. In addition, excellent endurance property till 10 ⁹ cycles with reduced wake-up effect was observed in HZO [1:3] capacitors with increasing the HPA temperature, while higher annealing pressure is found to increase P _r without affecting its endurance property. The results obtained herein can be of significant scientific importance, especially to achieve enhanced ferroelectric property with reduced wake-up effect in Zr-rich HZO ferroelectrics.