Si Chen

Following publication, the authors made an administrative error during submission

Microchannel liquid cooling technology, characterized by high heat-transfer efficiency, represents an effective solution for thermal management in high heat-flux density electronic devices. Existing research has mainly focused on optimizing the structural design of microchannel heat sinks, while neglecting the specific effects of inlet manifold configurations on their heat transfer and flow performance. To obtain more systematic data on microchannel heat transfer performance and internal velocity distribution, this study designed microchannels with single-inlet and triple-inlet configurations. A microchannel cooling performance testing platform was established, and visualization experiments of the internal flow field in straight microchannels were conducted using a particle image velocimetry (PIV) system. The velocity distribution uniformity and heat transfer performance were compared between single-inlet and triple-inlet microchannels with varying channel spacings. The results show that under the same flow conditions, the triple-inlet splitter structure yields a more uniform flow distribution, a lower peak temperature for the heat source chip, and improved heat transfer performance, with its pressure drop reduced to 11.1–26.6% of that of the single-inlet configuration. Furthermore, smaller channel spacings yield improved heat-transfer efficiency in microchannels.

The periodic thermal loads to which electronic devices are exposed during operation induce alternating thermal stresses due to the mismatched coefficients of thermal expansion (CTE) between the solder joints and the surrounding materials. This leads to cyclic thermal strain, ultimately causing crack initiation, propagation, and failure of interconnect structures. This study investigates thermal fatigue failure of Sn3.5Ag solder joints induced by cyclic thermal stresses from CTE mismatch. Numerical simulations and experiments reveal that alternating shear strain concentrates at the joint–pad interface, serving as the crack initiation site. This study proposes a hypothesis: extracting the equivalent viscoplastic strain range from the steady-state hysteretic response after cyclic stabilization and applying it to the Coffin–Manson model can mitigate the strain overestimation inherent to methods based on the initial transient impact, thereby providing a more reasonable physical basis for thermal fatigue life evaluation. Based on this, the thermal fatigue life of the solder joint is predicted to be 18,930 cycles. Analysis confirms significantly higher viscoplastic strain energy density at this critical point, indicating energy dissipation drives damage. This study addresses the above hypothesis from three aspects: deformation mechanism, cyclic response, and energy dissipation, providing a key basis for developing a highly reliable method for assessing solder joint life.

In this study, the stress–strain constitutive models of Cu-Cu joints in hybrid bonding after primary and secondary annealing were determined using nanoindentation experiments and finite element inverse analysis, and the correlation mechanism between the microstructure and macroscopic mechanical properties in hybrid bonding Cu-Cu joints during secondary annealing was revealed. The 350–400 °C secondary annealing facilitates recrystallization–grain growth, increasing grain size from 0.62 μm after primary annealing to 0.71 μm, accompanied by a 12% reduction in kernel average misorientation (KAM) values. This process enhances interface non-planarization and optimizes bonding quality. Concurrently, the secondary annealed Cu-Cu joints exhibit a softening effect, manifested by decreasing trends in elastic modulus (131.02 → 118.98 GPa), hardness (1.78 → 1.51 GPa), and yield strength (70.52 → 56.12 MPa), primarily attributed to the Hall–Petch effect and residual stress release. Notably, the yield strength of secondary annealed Cu-Cu joints demonstrates 31.0% and 68.5% enhancements compared to TSV-Cu (42.83 MPa) and bulk Cu (33.3 MPa), respectively.

Context Low-temperature Cu-Cu bonding is critical for 3D integration. Metal passivation layers promote this bonding, but their atomic mechanisms are not fully understood. Here, molecular dynamics simulations investigate how these layers enhance atomic diffusion and reduce bonding temperature. Results show that increasing temperature and time accelerate diffusion, temperature dominates diffusion via its exponential effect on the diffusion coefficient, while time linearly influences only the diffusion distance. The choice of metal passivation layer significantly influences the process. Titanium (Ti) most effectively facilitates diffusion. Initially, diffusion in the passivation layer resembles bulk metal interdiffusion, but over time, the formation of numerous and deeper grain boundaries within the passivation layer occurs, marking a shift toward low-energy grain boundary diffusion. It promotes low-temperature Cu-Cu bonding. Polycrystalline gold, with its initial grain boundaries, further accelerates diffusion and lowers the activation energy for bonding. Therefore, grain refinement is identified as an effective means of enhancing atomic diffusion and bonding quality. This work provides theoretical insights into lowering the temperature of Cu-Cu bonding and offers scientific foundations for optimizing bonding processes. Methods Molecular dynamics (MD) simulations using the LAMMPS package were conducted to study Cu-Cu bonding with various metal passivation layers (Ag, Au, Ti, polycrystalline Au). The Cu-passivation layer-Cu model was constructed, with atomic interactions described by the MEAM potential. Diffusion behavior was simulated under the NVT ensemble at target temperatures for 300 ps. The bonding interface evolution was visualized using OVITO, and diffusion coefficients and activation energies were derived from the mean square displacement (MSD), enabling inference of the passivation layer’s role in Cu-Cu bonding.

Packaging equipment plays a crucial role in the semiconductor industry by enhancing product quality and reducing labor costs through automation. Research was conducted on IGBT module packaging equipment (an automatic pin insertion machine) during the pin assembly process of insulated gate bipolar transistor (IGBT) modules to improve productivity and product quality. First, the manual pin assembly process was divided into four stages: feeding, stabilizing, clamping, and inserting. Each stage was completed by separate cams, and corresponding step timing diagrams are drawn. The profiles of the four cams were designed and verified through theoretical calculations and kinematic simulations using a seventh-degree polynomial curve fitting method. Then, image algorithms were developed to detect pin tilt defects, pin tip defects, and to provide visual guidance for pin insertion. Finally, a pin insertion machine and its human–machine interaction interface were constructed. On-machine results show that the pin cutting pass rate reached 97%, the average insertion time for one pin was 2.84 s, the pass rate for pin insertion reached 99.75%, and the pin image guidance accuracy was 0.02 mm. Therefore, the designed pin assembly machine can reliably and consistently perform the pin insertion task, providing theoretical and experimental insights for the automated production of IGBT modules.

This paper examined the reliability of complex PCB assemblies under random vibration and temperature cycling, which are two primary causes of assembly failure. A combination of finite element simulation and environmental testing was employed to investigate the effects of different reinforcement methods and solder joint morphology on assembly reliability. The linear accumulation of damage was utilized to predict assembly failure, and the predicted failure damage was compared with the damage extracted post-testing to validate the simulation analysis. The results indicate that SAC305 solder exhibits greater strength than Sn63Pb37 solder in withstanding temperature cycling fatigue, yet is weaker than Sn63Pb37 solder in withstanding random vibration fatigue. When the solder is Sn63Pb37, the temperature cycling life of the assembly with the bottom filled and the corners fixed is reduced by 92.3% and 99.3%, respectively, compared to the unreinforced method, while the random vibration life is enhanced by 84 times and 3.9 times, respectively. An increase in pad diameter is advantageous for improving the random vibration life of the assembly, but results in a decrease in the temperature cycling life. When the lower pad diameter ranges from 0.35 mm to 0.55 mm, the assembly temperature cycling life decreases by 28.83%, 82.03%, 90.66%, and 91.22% with the increase of the lower pad diameter, and the random vibration life improves by 4.8 times, 9.5 times, 20.4 times, and 33.6 times, respectively. The predicted locations of vulnerable solder joints for the assembly are consistent with the experimental results, and the failure prediction accuracy of the assembly is 88.89%.

In the 5G era, the demand for high-bandwidth computing, transmission, and storage has led to the development of optoelectronic interconnect technology. This technology has evolved from traditional board-edge optical modules to smaller and more integrated solutions. Co-packaged optics (CPO) has evolved as a solution to meet the growing demand for data. Compared to typical optoelectronic connectivity technology, CPO presents distinct benefits in terms of bandwidth, size, weight, and power consumption. This study presents an overview of CPO, highlighting its fundamental principles, advantages, and distinctive features. Additionally, it examines the current research progress of two distinct approaches utilizing Vertical-Cavity Surface-Emitting Laser (VCSEL) and silicon photonics integration technology. Additionally, it provides a concise overview of the many application situations of CPO. Expanding on this, the analysis focuses on the CPO using 2D, 2.5D, and 3D packaging techniques. Lastly, taking into account the present technological environment, the scientific obstacles encountered by CPO are analyzed, and its future progress is predicted.

Chip bonding, an essential process in power semiconductor device packaging, commonly includes welding and nano-silver sintering. Currently, most of the research on chip bonding technology focuses on the thermal stress analysis of tin–lead solder and nano-silver pressure-assisted sintering, whereas research on the thermal stress analysis of the nano-silver pressureless sintering process is more limited. In this study, the pressureless sintering process of nano-silver was studied using finite element software, with nano-silver as an interconnect material. Using the control variable method, we analyzed the influences of sintering temperature, cooling rate, solder paste thickness, and solder paste area on the residual stress and warping deformation of power devices. In addition, orthogonal experiments were designed to optimize the parameters and determine the optimal combination of the process parameters. The results showed that the maximum residual stress of the module appeared on the connection surface between the power chip and the nano-silver solder paste layer. The module warping deformation was convex warping. The residual stress of the solder layer increased with the increase in sintering temperature and cooling rate. It decreased with the increase in coating thickness. With the increase in the coating area, it showed a wave change. Each parameter influenced the stress of the solder layer in this descending order: sintering temperature, cooling rate, solder paste area, and solder paste thickness. The residual stress of the nano-silver layer was 24.83 MPa under the optimal combination of the process parameters and was reduced by 29.38% compared with the original value of 35.162 MPa.

With the advancement of Moore’s Law reaching its limits, advanced packaging technologies represented by Flip Chip (FC), Wafer-Level Packaging (WLP), System in Package (SiP), and 3D packaging have received significant attention. While advanced packaging has made breakthroughs in achieving high performance, miniaturization, and low cost, the smaller thermal space and higher power density have created complex physical fields such as electricity, heat, and stress. The packaging interconnects responsible for electrical transmission are prone to serious reliability issues, leading to the device’s failure. Therefore, conducting multi-field coupling research on the reliability of advanced packaging interconnects is necessary. The development of packaging and the characteristics of advanced packaging are reviewed. The reliability issues of advanced packaging under thermal, electrical, and electromagnetic fields are discussed, as well as the methods and current research of multi-field coupling in advanced packaging. Finally, the prospect of the multi-field coupling reliability of advanced packaging is summarized to provide references for the reliability research of advanced packaging.