Jiayao Ling
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Previous Organizations / Institutes
The organizations / institutes from the scholar's other articles in the past ten years
Research Subjects
Jiayao Ling has a total of 13 co-authors. Here are the top co-authors by number of shared publications:
- Cheng Gu
Shanghai Jiao Tong University
2 shared publications - Gang Li
Institute of Automation
2 shared publications - Jian Cheng
Institute of Automation, Chinese Academy of Sciences, Beijing, China
2 shared publications - Xiaolong Lin
Shanghai Jiao Tong University
2 shared publications - Xiaoyao Liang
Shanghai Jiao Tong University
2 shared publications - Jing Wu
Department of Applied Physics, Donghua University, Shanghai 201620, China
1 shared publication
Latest Publications
- 1 November 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 45 (11) , 6276-6289
Importance-Aware Dynamic Compression for Efficient Diffusion Models Inference
Diffusion models (DMs) exhibit remarkable generative performance within AI. Despite their outstanding generative capability, DMs still face two major limitations in fast and energy-efficient edge deployment: 1) the large number of parameters in DMs introduces substantial computational overhead during a single inference; 2) The iterative denoising property of DMs requires multiple inference steps, which further amplifies both computational and memory overhead. To alleviate the bottlenecks of DMs described above, we propose an importance-aware dynamic compression framework for hardware-efficient inference of DMs. We design importance metrics for steps, blocks, and layers in DMs based on the observation that not all denoising modules are equally important for a specific input. Guided by importance metrics, we propose a dynamic pruning method to eliminate redundant blocks during iterative denoising, while simultaneously applying binary quantization to the weights and mixed-precision quantization to the activations. To address the accuracy degradation introduced by the compression framework, we further propose tailored supervision losses and novel connection modes to improve the semantic fidelity and perceptual quality of the generated images. Given the binary and mixed-precision operations, along with the dynamic changes in model topology and computation flow due to pruning, we design a dedicated accelerator to more effectively supports our compression framework. Experimental results demonstrate that the proposed framework achieves a maximum pruning acceleration of 1.21× and a quantization bit-width of W2.05A4.59. The hardware implementation achieves 2.3× speedup and 76% energy savings compared to the baseline.
- 1 November 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 45 (11) , 6276-6289
Importance-Aware Dynamic Compression for Efficient Diffusion Models Inference
Diffusion models (DMs) exhibit remarkable generative performance within AI. Despite their outstanding generative capability, DMs still face two major limitations in fast and energy-efficient edge deployment: 1) the large number of parameters in DMs introduces substantial computational overhead during a single inference; 2) The iterative denoising property of DMs requires multiple inference steps, which further amplifies both computational and memory overhead. To alleviate the bottlenecks of DMs described above, we propose an importance-aware dynamic compression framework for hardware-efficient inference of DMs. We design importance metrics for steps, blocks, and layers in DMs based on the observation that not all denoising modules are equally important for a specific input. Guided by importance metrics, we propose a dynamic pruning method to eliminate redundant blocks during iterative denoising, while simultaneously applying binary quantization to the weights and mixed-precision quantization to the activations. To address the accuracy degradation introduced by the compression framework, we further propose tailored supervision losses and novel connection modes to improve the semantic fidelity and perceptual quality of the generated images. Given the binary and mixed-precision operations, along with the dynamic changes in model topology and computation flow due to pruning, we design a dedicated accelerator to more effectively supports our compression framework. Experimental results demonstrate that the proposed framework achieves a maximum pruning acceleration of 1.21× and a quantization bit-width of W2.05A4.59. The hardware implementation achieves 2.3× speedup and 76% energy savings compared to the baseline.
- 15 April 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 44 (11) , 4249-4262
An Efficient Bit-Sparse DNN Accelerator Exploiting Adaptive Bit-Serial Computations
Bit sparsity, an intrinsic attribute of binary representation, has been widely utilized in deep neural network (DNN) inference acceleration. Despite the advantages in performance and energy efficiency demonstrated by existing bit-serial-based bit-sparse accelerators, they still face two notable limitations: 1) at the low-level bit-serial multiplier level, existing methods either statically select weight or activation as the serialized object during the design phase, or simply serialize both without considering the distribution of nonzero bits in different operands, thereby failing to achieve optimal performance and 2) at the high-level dataflow level, existing approaches do not eliminate zero values in data movement and computation, leading to considerable energy and latency overhead, as well as suboptimal PE utilization. In this work, we propose AdaS-Pro accelerator for fast and energy-efficient DNN inference. At the multiplier level, AdaS-Pro employs an adaptive bit-serial computation scheme, which dynamically serializes the input operand with fewer nonzero bits at runtime, thereby minimizing compute cycles. To further enhance performance, AdaS-Pro introduces an improved Booth encoding method to reduce the number of nonzero bits in each operand. At the dataflow level, AdaS-Pro employs a compressed format to eliminate zero values and proposes a bi-directional inner-join unit coupled with a ring-shaped scheduler to achieve efficient nonzero workload extraction and balancing. Experimental results show that AdaS-Pro outperforms existing state-of-the-art bit-sparse accelerators, such as BitLet, BitX, and Laconic, with performance improvements of$4.03\times $ ,$6.78\times $ , and$1.43\times $ , respectively.- 15 April 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 44 (11) , 4249-4262
An Efficient Bit-Sparse DNN Accelerator Exploiting Adaptive Bit-Serial Computations
Bit sparsity, an intrinsic attribute of binary representation, has been widely utilized in deep neural network (DNN) inference acceleration. Despite the advantages in performance and energy efficiency demonstrated by existing bit-serial-based bit-sparse accelerators, they still face two notable limitations: 1) at the low-level bit-serial multiplier level, existing methods either statically select weight or activation as the serialized object during the design phase, or simply serialize both without considering the distribution of nonzero bits in different operands, thereby failing to achieve optimal performance and 2) at the high-level dataflow level, existing approaches do not eliminate zero values in data movement and computation, leading to considerable energy and latency overhead, as well as suboptimal PE utilization. In this work, we propose AdaS-Pro accelerator for fast and energy-efficient DNN inference. At the multiplier level, AdaS-Pro employs an adaptive bit-serial computation scheme, which dynamically serializes the input operand with fewer nonzero bits at runtime, thereby minimizing compute cycles. To further enhance performance, AdaS-Pro introduces an improved Booth encoding method to reduce the number of nonzero bits in each operand. At the dataflow level, AdaS-Pro employs a compressed format to eliminate zero values and proposes a bi-directional inner-join unit coupled with a ring-shaped scheduler to achieve efficient nonzero workload extraction and balancing. Experimental results show that AdaS-Pro outperforms existing state-of-the-art bit-sparse accelerators, such as BitLet, BitX, and Laconic, with performance improvements of$4.03\times $ ,$6.78\times $ , and$1.43\times $ , respectively.- Open Access
- 4 November 2019
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Access
- Vol. 7, 160345-160362
Design Method of Fabric Density Sensor Based on the Virtual Grating With Gradual Constant
In order to overcome the shortcomings of time-consuming and inefficient manual detection methods of fabric density, a fast and efficient automatic detection method of fabric density based on the digital grating is proposed. In order to realize automatic fabric density detection, the design method of the digital grating with gradual constant is described in detail on the basis of the principle of moiri pattern. The moiri pattern containing yarn density information of the fabric can be obtained by superimposing the captured fabric image and the digital grating image. After the moiri pattern is projected, the fabric density can be accurately determined by analyzing the distribution characteristics of projection curve. In the detection process, a digital grating image generated by computer is used to replace the physical grating, which not only makes the detection faster, but also make the system applicable for the fabric density detection of all kinds of specifications. Testing experiments were carried out on various fabric samples including fabrics in a plain weave and in a twill weave, the detection accuracy is more than 99.2 and the detection speed is much faster than the existing methods, which can meet the requirements of on-line detection in fabric production.
- 4 November 2019
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Access
- Vol. 7, 160345-160362
Open AccessDesign Method of Fabric Density Sensor Based on the Virtual Grating With Gradual Constant
In order to overcome the shortcomings of time-consuming and inefficient manual detection methods of fabric density, a fast and efficient automatic detection method of fabric density based on the digital grating is proposed. In order to realize automatic fabric density detection, the design method of the digital grating with gradual constant is described in detail on the basis of the principle of moiri pattern. The moiri pattern containing yarn density information of the fabric can be obtained by superimposing the captured fabric image and the digital grating image. After the moiri pattern is projected, the fabric density can be accurately determined by analyzing the distribution characteristics of projection curve. In the detection process, a digital grating image generated by computer is used to replace the physical grating, which not only makes the detection faster, but also make the system applicable for the fabric density detection of all kinds of specifications. Testing experiments were carried out on various fabric samples including fabrics in a plain weave and in a twill weave, the detection accuracy is more than 99.2 and the detection speed is much faster than the existing methods, which can meet the requirements of on-line detection in fabric production.