Yanlong Zhang

A fractional phase detector (PD) architecture that can significantly reduce the quantization error of a fractional-N phase-locked loop (PLL) is presented. It achieves instantaneous fractional phase detection by spatial averaging in the voltage domain through an array of reference-sampling PD (RSPD) cells. With this fractional PD, a prototype 5-GHz fractional-N RSPLL is implemented in a 65-nm CMOS process. Measurement results show that the in-band and out-of-band phase noises are reduced by 21 and 33 dB, respectively, leading to a significant reduction of the integrated rms jitter from 6.35 ps to 456 fs, almost the same as that at the integer-N mode (442 fs).

This brief presents a higher-order vector DEM for multibit discrete-time (DT) $\boldsymbol\Sigma\boldsymbol\Delta$ modulators ( $\boldsymbol\Sigma\boldsymbol\Delta$ Ms) to achieve higher linearity. By using the proposed vector filter (VF) with a poles-splitting technique, the root locus outside the unit circle of higher-order DEM can be eliminated, leading to the DAC mismatch-shaping stability will not be limited by the closed-loop poles of the vector DEM, thus a self-stabilizing vector DEM at higher order can be achieved. Besides, a complexity-reduced vector quantizer (VQ) using the segmented architecture is proposed. Compared to recent works, the proposed technique can achieve higher-order mismatch shaping and decouple the correlation between the mismatch errors and the input pattern, leading to stronger suppression of DAC mismatch and canceling in-band tones.

This brief describes a multi-phase injection-locked ring-VCO (MPIL-RVCO) with an improved phase noise (PN), while offering an inherent low-frequency output. Specifically, the MPIL-RVCO features dual oscillation loops, where the lowfrequency RVCO with substantial delay stages is integrated to reduce the 1/f3 phase noise corner (f1/f 3), whereas the multi-phase sub-outputs can serve to injection-lock the high-frequency output. The PN profile of the injection-locked high-frequency RVCO will up-shift with the injection signal, resulting in low f1/f 3. Prototyped in 65-nm CMOS, the proposed MPIL-RVCO operating at 2.88 GHz exhibits a PN of -96.2 dBc/Hz at 1-MHz offset, corresponding to a figure-of-merit (FoM) of 160 dBc/Hz and a low 1/f3 PN corner of 200 kHz.

This brief presents a 12-bit ultra-low-power asynchronous successive approximation register (SAR) analog-to-digital converter (ADC). A voltage-controlled delay line (VCDL) based open-loop time-domain comparator is proposed and analyzed, achieving low noise and ultra-low power performance. By employing the mixed switching scheme, the segmented capacitive digital-to-analog converter (CDAC) arrays as well as the synchronous data-weighted averaging (DWA) calibration block, the proposed SAR ADC can operate from 1.8 V down to 0.8 V at 20–200 kS/s. The designed ADC is fabricated in a 0.18- $\mu {\mathrm{ m}}$ CMOS process and the measurement results show the proposed SAR ADC achieves an SNDR of 65-dB with power consumption of 647 nW from a 0.8 V power supply at 20 kS/s.

This paper presents a highly digital technique that can significantly reduce the quantization noise of fractional-N phase-locked loops (PLLs) at all frequencies. This is achieved by using an array of dividers to realize spatial averaging. A fractional ΔΣ modulator (DSM) and a data-weighted averaging (DWA) module are used to generate the vector division ratio for the divider array. Based on this technique, a 2.4-GHz fractional-N frequency synthesizer is implemented in 40 nm CMOS process, in which spatial averaging is achieved with only one divider and phase selection to lower the power. Measurement results show that the phase noise at 1 MHz and 10 MHz frequency offsets are improved by 8 dB and 20 dB, respectively, compared to the conventional architecture. The output root-mean-square (rms) jitter is reduced from 10.4 ps to 3.1 ps, same as that at integer mode. The proposed synthesizer consumes only 4.9 mW in total, leading to a FoM of -223.3 dB.