Yongtae Kim

The Smith-Waterman algorithm guarantees optimal local alignment accuracy but suffers from quadratic time and memory complexity, limiting its scalability on large genomic datasets. To address this challenge, we propose a stride-based DNA sequence alignment accelerator that advances the alignment window by the read length rather than a single base, drastically reducing dynamic-programming updates while retaining alignment fidelity. Continuity across windows is preserved through overlap scoring and a multi-seed traceback mechanism that reconstructs boundary-spanning paths. A boundary-aware connection and output control further ensures consistent sequence reconstruction without rescoring interior cells. On DNA-to-DNA local alignment benchmarks using NCBI datasets, the proposed sequence aligner design achieves up to 0.98 similarity and 93.0% exact alignment rate, closely matching the exact Smith-Waterman baseline while offering over 100× higher throughput. Implemented in a 28-nm CMOS technology, the proposed accelerator delivers 29.9 Gbp/J energy efficiency and 2.41 Gbp/s/GE area efficiency, improving energy efficiency by 20.6× and throughput by 8.3× compared to the recent Smith-Waterman hardware accelerators. These results demonstrate that the stride-based computation can achieve biologically faithful alignments while enabling energy-efficient, high-throughput genomic analysis on modern embedded platforms.

Quantum arithmetic circuits, such as adders and multipliers, are essential for many quantum algorithms, but their practical deployment on noisy intermediate-scale quantum (NISQ) devices remains challenging due to limited coherence times and high gate error rates. In this paper, we propose Qaradox, a configurable approximate quantum multiplier architecture that achieves higher computation accuracy than its exact counterpart under realistic quantum noise. The proposed architecture introduces a novel class of controlled quantum adders that enable flexible combinations of exact, approximate, and truncated operations, allowing the quantum circuit to be tailored to hardware-specific noise characteristics. Experimental results using IBM’s 127-qubit Brisbane noise model show that Qaradox reduces the error rate (ER), normalized mean error distance (NMED), and mean relative error distance (MRED) by up to 23.7%, 80.3%, and 88.1%, respectively, compared to the fully exact multiplier. Furthermore, when applied to image sharpening, the proposed architecture improves peak signal-to-noise ratio (PSNR) by more than three times and increases structural similarity index measure (SSIM) from 0.00 to 0.83, effectively recovering visual quality lost in exact designs. These results demonstrate that approximation, when applied structurally and selectively, can enhance both robustness and correctness in quantum arithmetic for NISQ-era systems.

This letter presents novel approximate floating-point arithmetic units that leverage hardware-efficient rounding schemes to enhance computational accuracy while significantly improving hardware efficiency. By eliminating the need for guard, round, and sticky bits, the proposed designs achieve substantial reductions in area, power, delay, and energy up to 42.3%, 32.1%, 39.3%, and 58.8%, respectively, compared to conventional exact floating-point units implemented in a 28-nm CMOS technology. Experimental evaluations across multiple applications, including image processing, convolutional neural networks (CNNs), and spiking neural networks (SNNs), demonstrate that the proposed approach maintains high computational accuracy. Evaluations across image processing and neural network tasks show minimal quality and accuracy degradation, confirming the suitability of the proposed designs for energy-efficient applications.

Stochastic computing (SC) is an emerging computing paradigm that offers excellent hardware efficiency and error tolerance. However, adopting SC in practical applications is not straightforward but faces serious challenges. In particular, a considerable overhead is imposed by the conversion between binary number and stochastic counterpart, which is usually performed by a stochastic number generator (SNG) and a binary counter. In this paper, we address this overhead issue by introducing a novel quantized SC architecture that shrinks the SNG hardware complexity significantly and a new approximate binary counter. To do this, we quantize binary numbers for SNGs to lower precision counterparts through several bit truncation schemes, which leads to an SNG overhead reduction. Also, we exploit a small‐sized linear feedback shift register (LFSR) in the binary counter design to reduce its hardware resource consumption. When implemented in a 65‐nm CMOS technology, the proposed quantized SNG and approximate binary counter reduce area and power by up to 68.3% and 80.6%, respectively, compared to the conventional full‐precision SNG with an accurate counter. In addition, the proposed SC architecture with the LFSR‐based counter does not deteriorate the stochastic computation accuracy beyond a certain degree of quantization. Besides, we demonstrate that the proposed SC schemes negligibly impact on processing quality with remarkably improved hardware efficiency by adopting it in a digital image processing application.

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This letter presents a novel hardware-efficient approximate 4-2 compressor design that significantly enhances accuracy through a systematic analysis of input patterns obtained from practical applications. We incorporate a majority operation and a compound gate in the compressor design to effectively boost hardware efficiency in multiplications. Our design approach results in substantial error reductions, with normalized mean error distance (NMED) and mean relative error distance (MRED) decreasing by up to 74.84% and 82.04%, respectively, compared to existing approximate multipliers discussed in this letter. When implemented in a 32-nm CMOS technology, the approximate multiplier adopting the proposed 4-2 compressor achieves excellent hardware efficiency, reducing area, power, and energy consumption by up to 8.95%, 13.02%, and 13.02%, respectively, compared to the other alternatives. Moreover, our design delivers enhanced performance in image processing tasks, achieving up to a 4.84× increase in peak signal-to-noise ratio (PSNR) compared to other designs, all while optimizing hardware efficiency.