Vinay Ramakrishnaiah

With the ever-improving computation capability of GPUs, there is an increasing demand for higher memory bandwidth to supply the GPU cores with data. One way to improve effective memory bandwidth is with larger caches, and we have seen GPU vendors recently invest in very large last-level caches (LLCs). The key challenge is to maximize cache utilization and keep the active working set on-chip during the lifetime of a kernel. Software tiling optimizations can help, but programmers alone cannot anticipate dynamic cache capacity contention. To this end, we introduce the concept of cache cohorts: groups of kernels that share the same working set and thus can be efficiently scheduled together. Our approach uses the GPU command processor (CP) to track the occupancy of the LLC and throttles scheduling of the next cohort if there is no room. To evaluate the design space, we modify the existing GPU firmware on the AMD RX 7600 and RX 7900 XTX GPUs to prototype the scheduling scheme using real hardware. Our preliminary results show up to 27% reduction in execution time using the cache optimized scheduling technique on RX 7900 XTX.

With recent advances in deep learning and large-scale computing, learning-based controls have become increasingly attractive for complex physical systems. Consequently, developing generalized learning-based control software that takes into account the next generation of computing architectures is paramount. Specifically, for the case of complex control, we present the Easily eXtendable Architecture for Reinforcement Learning (EXARL), which aims to support various scientific applications seeking to leverage reinforcement learning (RL) on exascale computing architectures. We demonstrate the efficacy and performance of the EXARL library for the scientific use case of designing a complex control policy to stabilize a power system after experiencing a fault. We use a parallel augmented random search method developed within EXARL and present its preliminary validation and performance stabilization of a fault for the IEEE 39-bus system.

The U.S. Department of Energy's Office of Scientific and Technical Information

The multitiered iterative phasing (MTIP) algorithm is used to determine the biological structures of macromolecules from fluctuation scattering data. It is an iterative algorithm that reconstructs the electron density of the sample by matching the computed fluctuation X-ray scattering data to the external observations, and by simultaneously enforcing constraints in real and Fourier space. This paper presents the first ever MTIP algorithm acceleration efforts on contemporary graphics processing units (GPUs). The Compute Unified Device Architecture (CUDA) programming model is used to accelerate the MTIP algorithm on NVIDIA GPUs. The computational performance of the CUDA-based MTIP algorithm implementation outperforms the CPU-based version by an order of magnitude. Furthermore, the Heterogeneous-Compute Interface for Portability (HIP) runtime APIs are used to demonstrate portability by accelerating the MTIP algorithm across NVIDIA and AMD GPUs.

The U.S. Department of Energy's Office of Scientific and Technical Information

The U.S. Department of Energy's Office of Scientific and Technical Information

A novel method of Virtual Terrain Leveling (VTL) is proposed that virtually nullifies the effects of terrain on radio propagation using phased array antennas. This method has potential applications in avoiding interference in technologies like 5G, and ad hoc networks. Simulation results are provided to show the distribution of power for different terrains, and to highlight the benefits of using VTL.

Directional antennas shape transmission patterns to provide greater coverage distance and reduced coverage angle. When used in an ad-hoc network, this reduces interference among transmitting nodes and thereby increases throughput. A problem that has not been addressed is how to compute individual beam patterns that maximize some measure of global network performance. Historically, the focus has been on finding node antenna patterns that give locally optimal performance. In this paper we investigate a low hardware complexity beamforming approach aimed at improving global performance. Given a multi-hop route from source to destination, beam patterns are shaped to maximize average signal-to-noise ratio across all nodes on the route, which reduces bit-error rates and extends battery and network lifetime. By using phase-only weights, hardware costs are minimized.