Gustavo Della Colletta

This paper presents a real-time, low-power R-peak detector implemented in an FPGA. It is different from other implementations as it runs at the same signal sampling rate, rather than utilizing a high clock frequency as utilized in batch processing with high throughput systems. Such implementation relies on a Savitzky-Golay filter for power line noise filtering, and on an adapted version of the Difference Operation Method (DOM) algorithm. The modification in DOM is needed in order to be able to process the data either without increasing the clock to process data in a batch fashion or unsustainably increasing latency. It uses the Savitzky-Golay Digital Differentiator, eliminating further filtering stages. The prototype was characterized using both the MIT-BIH database and Fluke Prosim 8 Vital Signal Simulator. The proposed system features a high degree of matched R-peaks even being extremely efficient regarding power dissipation. Moreover, it shows similar performance when compared to the original Difference Operation Method implementation.The whole system consumes 260- uW operating at 192-Hz in an FPGA model 10M50DAF484C7G, which belongs to the MAX10 family of Altera devices.

This manuscript presents a fully differential difference transconductance amplifier (FDDTA) architecture based on CMOS inverters. Designed in a 130-nm CMOS process it operates in weak inversion when supplied with 0.25 V. In addition, the FDDTA requires no supplementary external calibration circuit, like tail current or bias voltage sources, since it relies on the distributed layout technique that intrinsically matches the CMOS inverters. For analytical purposes, we carried out a detailed investigation that describes all the concepts and the whole operation of the FDDTA architecture. Furthermore, a comparison between the modeling equations and measured data assures high performance.

This paper proposes using of a Savitzky-Golay digital differentiator (SGDD) in difference operation method (DOM) algorithm to detect QRS complex in an electrocardiographic monitoring system. Such modification enables using the SGDD low-pass feature to eliminate hardware filtering stages. Moreover, the SGDD also eliminates 60-Hz noise by choosing the proper window size and polynomial order. A Savitzky-Golay digital differentiator with thirteen samples window and third order polynomial, running at 360-Hz, increases the signal-to-noise ratio in 25 times. Performance has been evaluated by comparing the figures of merit for false positives, false negatives and true positives between both original DOM algorithm and the proposed modified one, showing notorious improvements.

This paper presents the use of Savitzky-Golay filter for power line interference cancellation in an embedded electrocardiographic monitoring platform. A Savitzky-Golay filter with eleven samples window and seventh order polynomial, running with a 192-Hz sampling rate, enables the matching of first zero crossing frequency in 60-Hz for a bandwidth of 40-Hz. These specifications satisfy the standard IEC 60601-2-27:2011. The arithmetical simplicity and the use of few integer coefficients allows the filter implementation in low-cost microcontrollers present in embedded electrocardiographic monitoring systems.

This work presents an architecture for Nauta fully differential operational transconductance amplifier that requires no additional circuitry for calibration. This design operates with a power supply of 0.25-V, implemented in a 130-nm digital CMOS process. By operating in the weak inversion region and using the transistor array approach, this OTA shows voltage reduction and stable gain using halo implanted transistors. The proposed OTA can operate at a voltage range from 0.15-V to 0.35-V, consuming only 6-nW to 333-nW of power and presenting a measured transconductance of 2.24-μS at 0.25-V. This makes it suitible for low-power G _m -C filters, such as biquad, which needs a wider range of frequencies (30-Hz to 6-kHz).

This paper presents a new SAR A/D conversion architecture that uses a PWM modulator and a first order low pass filter as alternative to conventional DAC implementations. Design equations were derived and a circuit implementation is proposed. In order to validate the proposed architecture, a 4bit successive approximation A/D converter has been designed and simulated. Then the circuit layout was developed in 0.5u m CMOS process with CADENCE Virtuoso. Post layout simulations were performed using BSIM3v3 model in Spectre simulator. DNL and INL erros are less then 0.1LSB. The power consumption is only 16u W for a 2.5V power supply.

This paper introduces a new architecture for a SAR A/D converter that uses the PWM technique in the internal DAC converter. One of the main disadvantages of traditional SAR ADCs is non-linearity, which degrades the DNL and INL parameters. Those errors are caused by the fabrication process. The proposed architecture aims to eliminate the process mismatches and thus minimizing the errors. In order to validate this architecture, a 4bit A/D converter has been simulated on Spectre simulator using BSIM3v3 model for a 0.5μ CMOS process. The power consumption is only 16μW for a power supply of 2.5V. The sample rate was limited to 200Hz, regarding the circuit design and the maximum frequency achieved by the CMOS process.