Yindong Xiao

As typical dynamic loads, electric vehicles (EVs) introduce significant uncertainty into distribution network operations due to the randomness of their travel behavior and charging demand. To achieve precise spatiotemporal forecasting of charging loads, this paper constructs a multi-dimensional transportation network model that accounts for dynamic road impedance factors and introduces a unit-distance energy consumption calculation method based on road impedance. By integrating the division of urban multifunctional zones and differentiated state-of-charge (SOC) threshold distributions across various EV types, a mapping model between travel chains and charging behaviors is established. Subsequently, large-scale travel and charging events are generated using an origin–destination (OD) probability matrix and Monte Carlo sampling to derive the spatiotemporal distribution of regional EV charging loads. Simulation results for a representative city in southwest China show that the predicted charging loads exhibit a dual-peak pattern, with significant differences across regions and vehicle types, and align well with observed load trends, validating the effectiveness and engineering applicability of the proposed method.

Integrated circuit (IC) test is a critical component in ensuring product quality, reliability, and cost control within the IC manufacturing process. Due to the increasingly integrated nature of system-on-chip (SoC) designs, the demand for studying mix-signal test in SoC dominates the chip test nowadays. While numerous test methodologies, such as structural test, IDDQ test, static or dynamic parameter characterization, and data processing, have been extensively studied, most of these focus on isolated test items for efficiency or fault coverage. Very limited work has been conducted on efficiency analysis across the entire manufacturing process. To address these limitations, this review synthesizes guidelines to reduce test costs while maintaining fault coverage throughout the entire test paradigm. Based on applicability, SoC test methods are primarily divided into three categories: direct test with automatic test equipment (ATE), test with design for test (DFT) technology, and failure analysis methods. To further assist researchers and engineers with diverse needs, these methods are subclassified by test objectives: rapid assessment, comprehensive diagnostics, and predictive analytics. Additionally, we introduce a novel metric, the extra information gain cost, to evaluate efficiency throughout the entire test process. Finally, the review highlights emerging research directions, such as aging prognosis and test in advanced package.

March algorithms are essential for detecting functional memory faults, characterized by their linear complexity and adaptability to emerging technologies. However, the increasing complexity of fault types presents significant challenges to existing fault detection models regarding analytical efficiency and adaptability. This article introduces the test primitive (TP), a unified notation that characterizes March test sequences through a novel methodology that decouples fault detection operations from sensitization states. The proposed TP achieves platform independence and seamless integration of fault models, supported by rigorous theoretical proofs. These proofs establish the fundamental properties of the TP in terms of completeness, uniqueness, and conciseness, providing a theoretical foundation that ensures the decoupling method reduces the computational complexity of March algorithm analysis to $O(1)$ . This reduction is analogous to Karnaugh map simplification in digital logic while enabling millisecond-level automated analysis. Experimental results demonstrate that the proposed method significantly enhances both analyzable fault coverage (FC) and detection accuracy, thereby addressing critical limitations of existing fault detection models.

The output bandwidth and the capacity to generate multiple analog outputs with high accuracy synchronization are essential specifications of an arbitrary waveform generator (AWG). The popularity of high-speed digital-to-analog converter (DAC) and high data throughput double data rate synchronous dynamic random-access memory (DDR SDRAM) has led to current AWG reaching the output wideband with GHz level. However, as the operating frequency increases, the signal propagation delay in the AWG becomes more sensitive to the clock signals, the trigger signal, and the channel differences, making the AWG’s output synchronization more challenging. For the accuracy synchronization of high-speed wideband AWG outputs, this article establishes a propagation model by analyzing the effects of clock signals, the trigger signal, and the channel differences on the propagation delay of waveform signals in the AWG channel. The corresponding synchronization design methods are discussed for each factor, and a synchronization structure of scalable multi-channel high-speed AWG is proposed. Furthermore, a channel delay adjustment technique based on the digital method is used to correct the time skew between outputs. Finally, an experimental platform for 8-channel AWG and 2-channel AWG has been designed according to the proposed method. Experimental results show that the number of output channels of AWG can be adjusted quickly according to the proposed scalable structure, and the synchronization accuracy can reach ±5 ps at 5 GSPS sampling rate.

In the design of SDRAM-based arbitrary waveform generators, the conflict between the randomness of dynamic memory output data flow and the requirement of seamless signal output is a non-negligible problem, especially in generators with hopping functions and high sampling rates. By imposing appropriate constraints in the design, the continuity of the output signal and the high throughput utilization can be guaranteed, and the constraints can be modeled to obtain the design boundary requirements under different specifications. In this paper, we analyze the throughput model of SDRAM and the access characteristics of an arbitrary waveform generator with jump capability. We establish a minimum waveform segment length model and a buffer size model to guarantee continuous signal output, which can obtain sufficient conditions for seamless synthesis of arbitrary waveform generators and be used to support the repeat/jump function of multi-segment waveforms. Experimental results on a DDR3 SDRAM-based generator show that the minimum waveform segment length obtained is within 11 words of the measured boundary, and the minimum buffer size is within 10 words of the measured boundary, which can effectively improve hardware resource utilization.