Jingtian Liu

This brief presents a fractional output divider (FOD) with a foreground digital-to-time converter (DTC) INL calibration scheme. This calibration scheme adjusts the delay control words of two main DTCs (mDTCs) to enable mutual comparison between them. By using a sign-least-mean-squares (sign-LMS) algorithm, the INL error codes are obtained and subsequently applied to a calibration DTC (cDTC) to compensate for the mDTC INL. The prototype occupies a compact core area of 0.01mm² and operates at a 0.9V supply with a power consumption of 3.6mW at 500MHz. Measurements demonstrate an integrated jitter of 512fs (10kHz to 20MHz) and spur level of -70dBc at 123.46MHz.

The power supply of LC-tank voltage-controlled oscillators (VCOs) demonstrates high sensitivity to single-event transients (SETs). This study presents a novel radiation-hardening-by-design (RHBD) technique that can automatically detect and mitigate SET disturbances. The proposed method incorporates additional floating well contacts to monitor fluctuations in well potential induced by heavy-ion strikes, serving as trigger signals for the RHBD circuitry. Operational amplifier (AMP) within low dropout regulator (LDO) circuit serve as an example to demonstrate the effectiveness of the proposed hardening technique for SET mitigation. Simulation results confirm the radiation tolerance of the RHBD LDO-VCO system operating at 27.35 GHz, using 28 nm bulk CMOS process. With proper configuration, the LDO-VCO can achieve complete immunity when subjected to heavy-ion impacts on sensitive nodes within AMP devices. This technique demonstrates broad applicability in the radiation-hardened design of analog integrated circuits for space applications.

This paper presents a single-event transient (SET) tolerant phase-locked loops (PLL) with a wide-tuning-range source-feedforward ring voltage controlled oscillator (SFRVCO), suitable for serial rapid I/O (SRIO). The analysis of impulse sensitivity function (ISF) shows that the proposed oscillator has lower phase noise, and its tuning range reaches 0.9-6.6GHz under the control of adjustable current source with high power supply rejection ratio (PSRR), which also exhibits better SET tolerance. Implemented in a 28nm CMOS process, the proposed SFRVCO achieves a phase noise of -96.7 dBc/Hz at 1 MHz offset from a 2.5 GHz carrier, occupying a core area of 0.0008 mm². Laser experiments indicate an irradiation threshold of 600 pJ.

Bandgap is a critical block for numerous electronic systems, which provides stable voltage reference for multiple sub-modules over process, voltage supply, and temperature (PVT) fluctuations. This paper firstly proposes a radiation-hardened-by-design (RHBD) technique which can automatically detect single-event transient (SET) disturbances and convert them into nanosecond-scale alternating signals, which can then be easily filtered by an on-chip filter. Theoretically, this technique can reduce SET amplitude to a negligible level regardless of bandgap structure and the output DC voltage. Laser experiments indicate that the SET pulse amplitude can be reduced from 896 mV to 48 mV under 800 pJ laser strike. This technique provides new guidance for SET mitigation on constant DC voltage and is widely applicable for bandgap radiation-hardening design.

Single-event transient (SET) glitches can be modified by body-biasing controlling techniques. In this article, a body-biasing configuration is proposed in combinational circuits, which plays no role during devices’ normal operation, but significantly mitigates SET disturbance as ion strike happens. NOR cell chains and NAND cell chains serve as cases to investigate the impact of the proposed configuration on SET vulnerabilities under two groups of heavy-ion experiments. Experimental data illustrate that transistors with body tied to source (BTS) significantly reduce the SET cross section compared with the normal designs. The physical mechanism of the proposed technique is quantitatively analyzed in detail.

Dynamic threshold-voltage MOSFETs (DTMOSs) with bulk and gate tied together are commonly used in ultra-low voltage applications. Since the threshold voltage of the device is a function of its gate voltage, and the current-driving capability is boosted as the gate-source voltage increases, it has the potential to be applied in the community of radiation-hardened IC circuits. This paper firstly demonstrates that DTMOS is particularly suitable for analog single-event transient (ASET) mitigation in cascode current mirrors with negligible penalty. A basic current mirror and a cascode current mirror are modelled to analyze the devices in DTMOS configuration, and compare radiation performance with standard MOSFETs. Simulation results demonstrate that the DTMOS scheme reduces charge collection, and suppresses single-event effect-induced perturbation effectively in the cascode current mirror, while playing a detrimental role in basic current mirrors due to the well-known bipolar effect. This technique provides a novel method for mitigating ASET disturbances for the designers of spaceborne ICs.

In nanometer bulk CMOS processes, multi-node charge collection induced by a heavy-ion strike is prevalent. Pulse quenching caused by charge sharing between the struck node (termed as active device) and the following gate (termed as passive device) has been widely studied in digital circuits. This paper firstly demonstrates that the pulse quenching effect also exists between the adjacent stages of analog circuits and can be used to mitigate analog single-event transient (ASET) perturbation. Contrary to digital circuits, whose propagated SET is minimized with the charge collected by passive device maximized, simulation results indicate that there is an optimal spacing between the active and passive devices in analog circuits. When the spacing is too close, the SET induced by the hit node is efficiently mitigated by pulse quenching effect, but the disturbance caused by the charge sharing collection in passive device becomes dominant. Simulation results show that pulse quenching effect has a dual role in ASET mitigation. This paper provides innovative guidance to the radiation-hardening design for analog circuits.

In analog circuit design, the bulks of MOSFETs can be tied to their respective sources to remove body effect. This paper models and analyzes the sensitivity of single-event transients (SETs) in common source (CS) amplifier with bulk tied to source (BTS) in 40 nm twin-well bulk CMOS technology. The simulation results present that the proposed BTS radiation-hardened-by-design (RHBD) technique can reduce charge collection and suppress the SET induced perturbation effectively in various input conditions of the circuit. The detailed analysis shows that the mitigation of SET is primarily due to the forward-bias of bulk potential. This technique is universally applicable in radiation-hardening design for analog circuits with negligible penalty.