Kasidit Toprasertpong

Ferroelectric Hf _{1− x} Zr _x O ₂ (HZO) is a promising high- k material for electron devices that requires high capacitance as it possesses a higher dielectric constant ( k -value). The capacitance–voltage ( C – V ) characteristics of HZO-based materials have been widely investigated near the quasi-static condition, while the behavior at high frequencies, where the ferroelectric polarization is likely to be a transient state, has not been understood well. In this study, we develop a fast C – V measurement method to evaluate the C – V characteristics of Hf _0.5 Zr _0.5 O ₂ films with various voltage sweep speeds, up to 400 V s ⁻¹ . The k -value of our 5.5 nm thick HZO extracted from the fast C – V measurement exhibits an enhancement at higher voltage sweep speed at the rate of 1.94 per decade of sweep speed, reaching k -value of 55.7 at the sweep speed of 400 V s ⁻¹ , as compared to 50.0 at 0.4 V s ⁻¹ . We attribute this phenomenon to the relaxation response of polarization to the abrupt change in the electric field. This finding reveals that the dielectric constant of high- k HZO films is governed by polarization dynamics, enabling a dynamically enhanced dielectric response under high frequency operation.

Photonic processors offer a promising approach to accelerating matrix multiplications, which dominate the workload in AI computations. Photonic matrix multiplication processors based on time-division multiplexing (TDM) have attracted significant interest due to their superior scalability, which is critical for realizing large-scale matrices with a limited number of on-chip optical components. To further enhance parallelism, wavelength-division multiplexing (WDM) can be incorporated, with each wavelength carrying different vector information. While several prior studies have demonstrated such photonic matrix processors using both TDM and WDM, the (de)multiplexing of multiple wavelengths is typically performed off-chip. In this work, we propose and demonstrate a hybrid WDM-TDM photonic matrix-matrix multiplication processor, which employs microring resonator (MRR) arrays as on-chip wavelength (de)multiplexers, achieving a higher level of integration compared with approaches that use off-chip (de)multiplexers. A 3-wavelength, 12-channel circuit is fabricated on a Si-on-insulator (SOI) platform and applied to handwritten digit recognition, achieving a classification accuracy of 93.2% on 2000 images. Furthermore, the scalability of wavelength multiplexing and computational performance are analyzed, providing design guidelines for scaling the proposed architecture.

Physical reservoir computing exploits inherent nonlinearity and short-term memory of physical dynamics to achieve efficient processing of time-series data with extremely-low training cost. In this study, we demonstrate a ferroelectric field-effect transistor (FeFET)-based reservoir computing system with augmented temporal and spatial nonlinearity by utilizing both gate and substrate terminals as inputs. The ferroelectric polarization state in the next time step can additionally be controlled by modifying the electric field distribution in the gate stack of FeFET through a substrate input, enabling more diverse internal states compared with the case where inputs are applied only to the gate. To introduce nonlinearity in the time domain, we introduce a delay between a gate input and a substrate input, which facilitates efficient nonlinear mixing between the current and past inputs. As a result, both the short-term memory and nonlinearity of the FeFET reservoir computing system are enhanced with an improved capability of feature extraction of complex input time-series. These findings demonstrate that introducing substrate input provides an additional degree of freedom for controlling ferroelectric polarization dynamics, enabling a flexible, energy-efficient, and highly integrable FeFET-based reservoir computing platform suitable for diverse time-series processing applications.

We demonstrate a low-loss and low-power InP MOSCAP optical phase shifter. The device features a MOSCAP structure formed by placing a metal electrode on top of an InP membrane waveguide, separated by a 700-nm-thick gate oxide. Voltage application induces electron accumulation at the surface of the InP waveguide, modulating the refractive index. By exploiting the large electron-induced refractive index change and the low free carrier absorption in InP, a modulation efficiency (V _π ·L) of 1.08 V·cm and an additional optical loss of 0.27 dB/π are obtained, despite the use of the thick gate oxide. Furthermore, the thick gate oxide suppresses leakage current, enabling low power operation of 11.5 pW/π.

Indium-based (In-based) oxide semiconductor channels fabricated by atomic layer deposition (ALD) become a promising candidate for back-end of line (BEOL) transistors and memory devices integrated with advanced CMOS technology. Although high reactivity plasma-enhanced ALD (PEALD) effectively removed the impurity ligands, the incorporation of excess oxygen into oxide semiconductor channels introduces the acceptor-like traps, which degrade device performance and bias stability. In this work, we characterize PEALD AlOx-passivated InOx FETs with channel thickness ranging from 1.8 to 2.6-nm, under different annealing ambient and temperatures. The 1.8-nm InOx FET subjected to oxidizing annealing shows current degradation, voltage hysteresis, and bias instability due to subgap trap formation caused by excess oxygen incorporation. Increasing the channel thickness to 2.6-nm mitigates these issues by reducing the interfacial effect from accumulated oxygen. This study provides design guidelines for BEOL-compatible oxide semiconductor FET fabricated by PEALD, enabling monolithic 3-dimensional integration.

We propose III-V/Si hybrid plasmonic waveguide photodetector incorporating an InGaAs membrane. We confirmed that Ni-InGaAs alloy functions effectively as an electrode for a plasmonic waveguide. Utilizing Ni-InGaAs alloy enabled the integration of plasmonic waveguide photodetectors into the Si photonics platform through a simplified fabrication process. We achieved a responsivity of 0.13 A/W at 1 V with a dark current of 400 nA and confirmed a 32.1 Gbit/s clear eye diagram, demonstrating the potential for high speed InGaAs plasmonic photodetector in Si photonics.

We study MOS capacitors on vicinal Si(110) substrates to evaluate the influence of off-angle on the SiO ₂ /Si interface properties by using the conductance method and the high-low frequency method. We examine the (100) orientation with no off-angle and the (110) orientation with seven different off-angles, 0°, 0.19°, 0.27°, 0.33°, 0.78°, 1.0°, and 8.0° ((551) orientation). Across all (110) off-angles, the fixed charge density and the surface potential fluctuation show no significant dependence on off-angles. Although the interface trap density exhibits a slight dependence on off-angles, the trend is insignificant when considering MOSFET performance. These results suggest that slight off-angle deviation does not critically affect the interface properties of (110) surfaces, offering process robustness and design flexibility in (110)-channel MOSFETs. In addition, the (551) surface exhibits a lower interface trap density compared to (110) surfaces with smaller off-angles, indicating its potential for high-quality interfaces.

We propose and demonstrate a novel four-port evanescently coupled Ge-on-Si photodetector (PD) designed to overcome performance limitations under high optical power. This study aims to mitigate the space-charge effect that causes photocurrent saturation and bandwidth degradation in conventional Ge-on-Si PDs. In our device, the input optical signal is divided into four waveguides that evanescently couple light into a central Ge absorption region from four sides. This configuration effectively distributes the optical intensity, thereby reducing the space-charge effect. The fabricated PD exhibits a linear responsivity of 1.08 A/W, a large maximum photocurrent of 54 mA, and a 3-dB bandwidth of approximately 15 GHz at an output current of 15 mA. These results indicate that the proposed PD offers a promising solution for high-power and high-speed applications, demonstrating strong potential for advanced radio-frequency photonics.

The improvement in electrical properties of bottom-gate AlO $_{\textit{x}}$ -passivated 1.8-nm-thick InO $_{\textit{x}}$ FETs by inserting a 1.1-nm thick AlO $_{\textit{x}}$ interlayer between the oxide channel and HfO $_{\textit{x}}$ dielectric is experimentally investigated. The ultrathin AlO $_{\textit{x}}$ interlayer prevents impurities diffusion from the HfO $_{\textit{x}}$ layer into InO $_{\textit{x}}$ channels during fabrication, which can address the negative initial ${V}_{\text {th}}$ issue in devices with single-HfO $_{\textit{x}}$ dielectric. The InO $_{\textit{x}}$ FETs with AlO $_{\textit{x}}$ /HfO $_{\textit{x}}$ dielectric provide a positive threshold voltage ( ${V}_{\text {th}}\text {)}$ of 0.22V and the subthreshold swing (SS) of 65.8 mV/dec after annealing in N₂ ambient at $300~^{\circ }$ C. Due to the reduction of interface trap density and the number of fixed charges by an ultrathin AlO $_{\textit{x}}$ interlayer, devices with $300~^{\boldsymbol {\circ }}$ C annealing show excellent positive and negative bias instability of 52 and 58 mV for 3-h stressing at a ${V}_{\text {g}}-{V}_{\text {th}}$ of $\boldsymbol {\vert }{{1}}{\,}\text{V} \boldsymbol {\vert }$ , respectively. Finally, the possible mechanisms of bias stress instability in InO $_{\textit{x}}$ FETs with AlO $_{\textit{x}}$ /HfO $_{\textit{x}}$ dielectric are discussed.