Jian Hu

The growing demand for sophisticated applications has driven a surge in circuit complexity, consequently raising the probability of design errors. This trend underscores the need for automated and effective debugging solutions. Large Language Models (LLMs) have shown strong analytical capabilities in program understanding and debugging, offering a novel perspective for bug localization in Register Transfer Level (RTL) designs. In this paper, we propose LocFree, a LLM-based framework for bug localization in RTL designs using hierarchical reasoning. LocFree comprises two main phases: the prompt generation phase and the bug localization phase. In the prompt generation phase, LocFree extracts four critical features from the Verilog code and its corresponding testbench: metadata feature, semantic structure feature, timing pattern feature, and testbench feature. It then employs these features in a hierarchical reasoning process to generates an optimized prompt that guides the LLM toward precise bug localization. In the bug localization phase, LocFree leverages the optimized prompt in conjunction with the LLM to identify the faults in the RTL designs. Experimental evaluation on 26 Verilog designs containing 397 bugs demonstrates that LocFree significantly outperforms state-of-the-art techniques. Specifically, our approach successfully localizes 76.8%, 82.5%, and 87.3% of bugs within the Top-1, Top-3, and Top-5 ranks, respectively—substantially exceeding the performance of existing bug localization methods.

Hardware verification of the register transfer level (RTL) designs is a critical step in the development of complex digital circuits, ensuring their functional correctness, performance, and reliability. Within this crucial process, bug localization is an essential component for precisely identifying the root causes of design errors. Dynamic bug localization (DBL) stands out as an efficient and automatic approach to locate bug source code by calculating statement suspiciousness based on execution traces. However, DBL methods rely solely on coverage information and simplistic statistical formulas to compute suspiciousness, which has been criticized for their limited precision and inadequate reduction of debugging effort. In this paper, we propose MulFetFL: a multi-features deep learning based bug localization for RTL designs. MulFetFL begins by extracting three multimodal features: abstract syntax tree (AST) features, signal features, and timing features from designs. It then employs Graph Attention Networks (GAT) to enhance node representations. A cross-modal attention mechanism is subsequently applied to fuse these complementary features from different modalities. Finally, the fused features are passed through a multi-layer perceptron (MLP) to compute the suspiciousness score for each statement. Experimental results show that MulFetFL effectively locates 293, 295 and 298 bugs within Top-1/Top-3/Top-5 ranks, significantly outperforming state-of-the-art bug localization methods across a range of benchmark designs.

Coincidental Correctness (CC) arises when a test case executes faulty entity in a program without causing a failure. This phenomenon injects noise into coverage information, as CC tests weaken the connection between faulty entities and test failures. Since many fault localization (FL) approaches relies on analyzing test execution traces to locate faulty entities, the compromised reliability of test results directly undermines FL accuracy. Furthermore, the detrimental effects of CC extend beyond fault localization to subsequent software maintenance tasks like automatic program repair. Therefore, identifying and mitigating CC tests becomes critical not only for enhancing FL but also for ensuring robust software quality assurance. Thus, we propose FusionCC: an approach that applies multiscale coverage features and handcrafted features to fuse complementary feature representations for CC test case detection. Specifically, FusionCC first refines original coverage data by filtering out noisy irrelevant elements, then extracts multiscale features from the refined matrix, and finally fuses the coverage and handcrafted features to generate highly informative feature representations for CC detection. FusionCC realizes a comprehensive fusion of complementary features across different scales and from diverse sources, which significantly enhances the accuracy of CC detection. To evaluate the effectiveness of FusionCC, we conduct large-scale experiments on 277 faulty versions of six representative benchmarks. The experimental results show that FusionCC significantly improves CC detection (e.g., average improvements of 50.93% precision and 82.03% in $F_{1}$ value compared to state-of-the-art CC detection approaches) and fault localization effectiveness (e.g., 10.33, 19.33, 25.67 average faults can be found in terms of Top-1, Top-3, Top-5 metrics at relabel strategy compared with state-of-the-art FL approaches).

Verification is crucial in hardware code development as it ensures the design behaves as intended under all possible conditions, meeting its functional and performance specifications. Bug localization plays a vital role in the verification of hardware code by identifying the precise source of errors detected during simulation, testing, or formal analysis. Dynamic bug localization is a debugging technique that has gained attention in both software and hardware domains. It aims to automatically identify the most likely sources of errors in a design by analyzing the relationship between code coverage (or signal activity) and test outcomes (pass/fail). Despite its promise, DFL in hardware faces several challenges, including the abundance of bug-irrelevant statements, the limited expressiveness of coverage information, and the constrained learning capacity of simple statistical formulas. In this article, we propose Laurel, a l earning-to-r a nk fa u lt localization method for ha r dwar e code using mu l ti-feature fusion. To overcome the existing limitations in DFL, Laurel employs a value dependence graph (VDG) to effectively filter out bug-irrelevant statements. It further enhances semantic feature representation by extracting and fusing multiple features. Finally, a learning-to-rank model is then employed to learn the fused features and compute the suspiciousness score of each statement. We validate the effectiveness of Laurel through comprehensive experiments, comparing it against the state-of-the-art DFL methods on large-scale hardware benchmarks. Results demonstrate that Laurel substantially outperforms all the state-of-the-art DFL methods, achieving an average improvement of 384.6% in Top-1 accuracy for Tartan.

The maintenance of quality and reliability in hardware products inherently relies on the verification of hardware code. Despite being a time-consuming process, the localization of faults in hardware code is essential for effective hardware verification. Dynamic fault localization (DFL) is considered one of the most effective methods for localizing faults. It utilizes coverage information, known as the coverage matrix, which is obtained from both passing and failing tests, to identify the program elements that are most likely responsible for observed failures in hardware programming languages such as VHDL or Verilog. However, the presence of error propagation, numerous fault-irrelevant statements, and highly imbalanced coverage information pose significant challenges for DFL. In this article, we propose Canal, a C ontext- a ware data augme n tation a pproach for dynamic fau l t localization in hardware code, to address these challenges. Canal effectively overcomes these challenges by leveraging in-time detection to prevent error propagation and utilizing program slicing to construct a semantic context that filters out fault-irrelevant statements. Additionally, it employs over-sampling techniques to balance the coverage information of passing and failing tests. Finally, the balanced coverage matrix is fed into DFL to compute the suspiciousness value of each statement. To evaluate the effectiveness of Canal, we conduct large-scale experiments on 10 programs and compare our method with 10 dynamic fault localizations. The experimental results clearly demonstrate that Canal surpasses the performance of all the compared DFL methods; e.g., Canal achieves an average improvement of 148.2% in Top-1 accuracy compared to the evaluation formulas.