Yi Wan

Aggressive scaling in silicon electronics—although essential for improving power, performance, area and cost—faces increasing challenges in further reducing power consumption due to electrostatic and leakage constraints ^1,2 . Achieving efficient operation at low supply voltages therefore requires new materials and gate-stack engineering strategies. Two-dimensional (2D) semiconductors offer intrinsic advantages because their atomic thickness affords excellent gate control, and their sizable bandgaps suppress off-state current. However, a major obstacle is the imperfect interface between 2D channels and gate dielectrics, which degrades subthreshold swing, hysteresis and bias-temperature instability ³ . Here we demonstrate that a wafer-scale, transferable, single-crystal anatase titanium dioxide dielectric can be van der Waals integrated with 2D transition metal dichalcogenides. The obtained pristine 2D-dielectric interface enables subthreshold swing close to the thermal limit, record-low hysteresis and well-matched transfer characteristics for both n- and p-type enhancement-mode field-effect transistors. Building on this, we demonstrate complementary field-effect transistors, whose inverters achieve high voltage gain and large noise margins with subpicowatt static power consumption. These results highlight the promise of 2D semiconductors for ultra-low-power operation.

Transistors based on two-dimensional (2D) materials are on the roadmap for the beyond 1 nm logic technology node¹. This stems from their ultrathin thickness and defect-free surfaces, granting remarkable electrostatic gate control^2-5. The physical channel length of 2D transistors may eventually reach 2 transistor. This approach allows contact scaling constraints to be determined, providing information for the development of future ultra-scaled electronic devices.

As silicon transistors scale toward future technology nodes, three-dimensional architectures-including gate-all-around (GAA) nanoribbon and complementary field-effect transistors (CFETs)-require channel widths in the tens of nanometers to meet density targets. Monolayer transition metal dichalcogenides (TMDs), with their atomically thin bodies, are promising channel materials for these architectures, yet most TMD-based FETs remain limited to micrometer-scale widths. Here, we show that channel width scaling of monolayer MoS₂ nanoribbon transistors not only preserves but also enhances device performance. Reducing the channel width from hundreds of nanometers to ~30-40 nm increases the median on-current density by ~42% and reduces the median subthreshold swing by ~16%, with a champion device reaching 995 µA µm^-1 at a drain-to-source voltage of 1 V and an overdrive voltage of 2.5 V. We attribute these improvements to three mechanisms: minimal edge-induced disorder, enhanced gate electrostatics at ribbon edges, and more efficient side-contact injection, together reducing contact resistance from ~860 Ω µm to ~270 Ω µm. Extending the platform to n-type WS₂ and p-type WSe₂ FETs, we achieve WSe₂ p-FET on-currents of 357 µA µm^-1. These findings suggest that monolayer TMD nanoribbon FETs are promising candidates for future ultra-scaled electronics.

Strain engineering offers a powerful route to modulate the electronic structure and light–matter interactions in 2D semiconductors. However, existing approaches largely rely on flexible substrates or mechanically complex micro‐electromechanical platforms, which limit scalability, reconfigurability, and on‐chip integration. Here we introduce an in‐plane isolated gated architecture that establishes strong lateral electrostatic fields across a suspended monolayer MoS ₂ , delivering large‐range, tunable, and reversible in‐plane uniaxial strain without any other moving parts, by harnessing the electro‐elastic coupling originating from in‐plane symmetry breaking. In situ photoluminescence quantifies a monotonic bandgap tuning from 1.83 eV to 1.66 eV under electrostatic field modulation, corresponding to over 3% in‐plane strain. With this platform, strain contrast between suspended and supported domains forms an addressable homojunction governed by field magnitude and channel orientation. This strain‐defined junction exhibits rectification behavior and a tunable photoconductive cutoff wavelength spanning 640 to 785 nm. Leveraging these properties, a single standalone device achieves wavelength‐division multiplexing signal separation and polarization‐resolved photodetection without external optical components. These results suggest electrostatic‐field‐induced strain as a promising, scalable, and CMOS‐compatible mechanism for operando localized strain engineering in 2D materials, provides a general route to unlock capabilities in spectral sensing, polarization‐aware detection, and compact optical interconnects.