Jinjuan Xiang

2023 International Conference on Solid State Devices and Materials ,Impact of the dielectric layer on Wake-up Effect of HZO-based Thin Films

2023 International Conference on Solid State Devices and Materials ,Characterization of Metal/IGZO Contact with Back-to-Back Schottky Diode

This work investigates the endurance characteristic of Si FeFET with Hf $_{\text{0.5}}$ Zr $_{\text{0.5}}$ O $_{\text{2}}$ ferroelectric. A fully CMOS-compatible method is shown to improve endurance: insertion of the thin HfO $_{\textit{x}}$ layer ( $\sim$ 2–5 Å) at the Hf $_{\text{0.5}}$ Zr $_{\text{0.5}}$ O $_{\text{2}}$ /SiO $_{\textit{x}}$ interface. The ab initio calculations prove that the HfO $_{\textit{x}}$ insertion can increase the formation energies of oxygen vacancies and suppress their generation in the gate stacks and, consequently, improve the endurance. This method paves a possible path to improve the endurance of Si FeFET.

This work investigates trap generation in gate stacks of ferroelectric field-effect transistor (FeFET) with TiN/Hf $_{\text{0.5}}$ Zr $_{\text{0.5}}$ O $_{\text{2}}$ /SiO $_{\textit{x}}$ /Si gate structure during endurance fatigue by using the low-frequency noise method. We find that the traps are generated not only at Hf $_{\text{0.5}}$ Zr $_{\text{0.5}}$ O $_{\text{2}}$ /SiO $_{\textit{x}}$ interface but also in both the Hf $_{\text{0.5}}$ Zr $_{\text{0.5}}$ O $_{\text{2}}$ and SiO $_{\textit{x}}$ . Our work provides evidence of defect generation inside the ferroelectric layer of FeFET during cycling. Furthermore, the traps in the SiO $_{\textit{x}}$ are more detrimental to endurance fatigue. And the trap generation in the SiO $_{\textit{x}}$ is more important than its initial trap density for endurance fatigue. Our work is helpful in deeply understanding the endurance of FeFET.

A novel 3D NOR memory array with single-crystal silicon channel, high-density and fast-read was proposed and fabricated. The proposed 3D NOR memory is investigated in terms of device structure, integration scheme, and circuit architecture. To obtain single-crystal silicon channel for 3D NOR, 1) vertical flash devices were presented, 2) a stack with multiple doped epitaxial Si layers was used for making the vertical devices, and 3) unlike 3D NAND, bit-line planes, source-line planes and vertical word-lines were utilized. Due to the use of single-crystal silicon channels, our memory devices have large read currents of $110 ~\mu \text{A}/\mu \text{m}$ . Through programming/erasing tests, the programming speed of $10 ~\mu \text{s}$ and erasing speed of 100 ms were obtained, which are comparable to that of the 2D NOR Flash with single-crystal silicon channels.

A novel vertical C-shaped-channel nanosheet field-effect-transistor (VCNFET) featured with precise control of channel-thickness and gate-length, and a unique integration flow of Dual Side Process (DSP) are proposed in this work. The VCNFETs were fabricated by high quality Si/SiGe epitaxy, atomic layer etching with nanometer-scale process control and self-aligned high-k metal gate (HKMG). The integration flow is compatible with mainstream CMOS technology. Thanks to the precise control of channel thickness and doping profiles, perfect SS of 61 mV/dec, small DIBL of 8 mV/V, and remarkably large $\text{I}_{\text {on}}/\text {I}_{\text {off}}$ ratio of ${6.28}\times {10}^{{9}}$ were achieved. The device performance and it’s optimization were also investigated with the reduction of the external resistance and numerical simulations.

The ferroelectric field-effect transistor (FeFET) is a promising candidate for emerging memory. However, data retention loss is a key issue. One reason for the data retention loss is the depolarization field ( ${E}_{dep}$ ). In this work, we theoretically investigate ${E}_{dep}$ of ferroelectric transistors with the metal/Hf _0.5 Zr _0.5 O ₂ /SiO ₂ /Si substrate (MFIS) gate structure considering the minor loop and charge trapping effect at the ferroelectric/interlayer interface. We find that ${E}_{dep}$ increases first and then decreases with the increased interlayer thickness ( ${t}_{IL}$ ). The charge trapping phenomenon will decrease ${E}_{dep}$ and make ${t}_{IL}$ at which ${E}_{dep}$ reaches the peak value larger. To design a ferroelectric transistor considering both the depolarization field and the memory window, different schemes about how to choose suitable interlayer and ferroelectric layer thicknesses in three different regions need to be adopted.

In this work, a p-type high- ${k}$ metal gate (HKMG) with 3-nm interfacial Al ₂ O ₃ doping HfO ₂ laminated dielectric is presented to achieve the required gate electrode effective work function (EWF). Through the ex-situ interfacial doping strategy with various Al ₂ O ₃ thickness, the electrical and interface characteristics of p-type HKMG MOSCAP are investigated. The results show that these parameters are strongly dependent on the thickness of the Al ₂ O ₃ . By increasing the Al ₂ O ₃ thickness, the flat-band voltage ( ${V}_{\text {FB}}$ ) positive shift is elevated by 360 mV, and the trap/detrap electrons density ( ${N}_{\text {ot}}$ ) is significantly suppressed by an order of magnitude. In addition, the interface charge density ( ${N}_{\text {SS}}$ ) is significantly reduced, and interface trap density ( ${D}_{\text {it}}$ ), time-dependent dielectric breakdown (TDDB), and positive bias stress (PBS) is obviously improved. Finally, EWF modulation was increased from 4.976 to 5.206 eV (over the valence band edge of 5.17 eV). The results reveal that it is possible to tailor dielectric and electrical properties of high- ${k}$ layers by adding a proper amount of interfacial Al ₂ O ₃ doping into HfO ₂ , meeting the criteria required for gate electrode p-type EWF. These results and discussion provide an effective method for the integration of the HKMG stack in the MOSFETs and also useful for design of CMOS integration.

We investigate the charge trapping during endurance fatigue of FeFET with TiN/Hf _0.5 Zr _0.5 O ₂ /SiO ₂ /Si (MFIS) gate structure. We propose a method of experimentally extracting the number of trapped charges during the memory operation, by measuring the charges in the metal gate and Si substrate. We verify that the amount of trapped charges increases during the endurance fatigue process. This is the first time that the trapped charges are directly experimentally extracted and verified to increase during endurance fatigue. Moreover, we model the interplay between the trapped charges and ferroelectric polarization switching during endurance fatigue. Through the consistency of experimental results and simulated data, we demonstrate that as the memory window (MW) decreases: 1) the ferroelectric characteristic of Hf _0.5 Zr _0.5 O ₂ is not degraded; 2) the trap density in the upper bandgap of the gate stacks increases; and 3) the reason for MW decrease is increased trapped electrons after program operation but not related to hole trapping/detrapping. Our work is helpful to study the charge trapping behavior of FeFET and the related endurance fatigue process.

Ge has been an alternative channel material for the performance enhancement of complementary metal–oxide–semiconductor (CMOS) technology applications because of its high carrier mobility and superior compatibility with Si CMOS technology. The gate structure plays a key role on the electrical property. In this paper, the property of Ge MOSFET with Al₂O₃/GeO _x /Ge stack by ozone oxidation is reviewed. The GeO _x passivation mechanism by ozone oxidation and band alignment of Al₂O₃/GeO _x /Ge stack is described. In addition, the charge distribution in the gate stack and remote Coulomb scattering on carrier mobility is also presented. The surface passivation is mainly attributed to the high oxidation state of Ge. The energy band alignment is well explained by the gap state theory. The charge distribution is quantitatively characterized and it is found that the gate charges make a great degradation on carrier mobility. These investigations help to provide an impressive understanding and a possible instructive method to improve the performance of Ge devices.