James Garland

In deep metric learning (DML) high-level input data are represented in a lower-level representation (embedding) space, such that samples from the same class are mapped close together, while samples from disparate classes are mapped further apart. In this lower-level representation, only a single inference sample from each known class is required to accurately discriminate between classes. To this end, embeddings trained for a specific task may contain additional feature information which can be used to go a level deeper into the discrimination task, i.e. allowing for feature sub-discrimination. This study takes an embedding trained to discriminate faces (identities) and uses the inherent feature information within the embedding to differentiate several attributes such as gender, age, and skin tone, without any additional training. This study is split into two cases; intra class discrimination where all the embeddings considered are from the same identity/in-dividual but with minor attributes such as beard/beardless, glasses/without glasses and emotions; and extra class discrimination where the embeddings represent different identities/people with more prominent attributes such as male/female, pale/dark tone, young/older. In the intra class sub-discriminant scenario, the inference process distinguishes common attributes and several artefacts of different identities, achieving 90.0% and 76.0% accuracy for beards and glasses, respectively. The system can also perform extra class sub-discrimination with a high accuracy rate, notably 99.3%, 99.3% and 94.1% for gender, skin tone, and age, respectively. To sum up, this work investigates the sub-discriminative capabilities of DML models by clustering discriminative features evident within the structure of DML embeddings.

Visual inspections of aircraft are a vital part of routine procedures for maintenance personnel in the aviation industry. However, visual inspections take up a considerable amount of time to perform and are susceptible to human error. To mitigate this, utilising image classification for detecting defects is proposed. This approach utilises transfer learning of ResNet-50 within MATLAB to determine whether a defect is present in an image taken of the aircraft. The proposed method offers a solution for improving the efficiency and accuracy of defect detection during a general visual inspection in the aviation industry. Targeted defects here are damaged_skin and missing_rivets alongside a class denoting no_defect. Validation and testing accuracies achieved in this study are 88.33 % and 65.55 %, respectively.

Low-precision floating-point (FP) can be highly effective for convolutional neural network (CNN) inference. Custom low-precision FP can be implemented in field programmable gate array (FPGA) and application-specific integrated circuit (ASIC) accelerators, but existing microprocessors do not generally support fast, custom precision FP. We propose hardware optimized bitslice-parallel floating-point operators (HOBFLOPS), a generator of efficient custom precision emulated bitslice-parallel software(C/C++) FP arithmetic. We generate custom-precision FP routines, optimized using a hardware synthesis design flow, to create circuits. We provide standard cell libraries matching the bitwise operations on the target microprocessor architecture and a code generator to translate the hardware circuits to bitslice software equivalents. We exploit bitslice parallelism to create a novel, very wide (32—512 element) vectorized CNN convolution for inference. On Arm and Intel processors, the multiply-accumulate (MAC) performance in CNN convolution of HOBFLOPS, Flexfloat, and Berkeley’s SoftFP are compared. HOBFLOPS outperforms Flexfloat by up to 10× on Intel AVX512. HOBFLOPS offers arbitrary-precision FP with custom range and precision, e . g ., HOBFLOPS9, which outperforms Flexfloat 9-bit on Arm Neon by 7×. HOBFLOPS allows researchers to prototype different levels of custom FP precision in the arithmetic of software CNN ac celerators. Furthermore, HOBFLOPS fast custom-precision FP CNNs may be valuable in cases where memory bandwidth is limited.

In recent years, deep neural networks (DNNs) have emerged as the most successful technology for many difficult problems in image, video, voice and text processing. DNNs are resource hungry and require very large amounts of computation and memory, which is a particular challenge on IoT, mobile and embedded systems. In this chapter, we outline some major performance challenges of DNNs such as computation, parallelism, data locality and memory requirements. We describe research on these problems, such as the use of existing high-performance linear algebra libraries, hardware acceleration, reduced-precision storage and arithmetic and sparse data representations. Finally, we discuss recent trends in adapting compiler and domain-specific program generation techniques to create high-performance parallel DNN programs.

Convolutional neural networks (CNNs) are one of the most successful machine-learning techniques for image, voice, and video processing. CNNs require large amounts of processing capacity and memory bandwidth. Hardware accelerators have been proposed for CNNs that typically contain large numbers of multiply-accumulate (MAC) units, the multipliers of which are large in integrated circuit (IC) gate count and power consumption. “Weight-sharing” accelerators have been proposed where the full range of weight values in a trained CNN are compressed and put into bins, and the bin index is used to access the weight-shared value. We reduce power and area of the CNN by implementing parallel accumulate shared MAC (PASM) in a weight-shared CNN. PASM re-architects the MAC to instead count the frequency of each weight and place it in a bin. The accumulated value is computed in a subsequent multiply phase, significantly reducing gate count and power consumption of the CNN. In this article, we implement PASM in a weight-shared CNN convolution hardware accelerator and analyze its effectiveness. Experiments show that for a clock speed 1GHz implemented on a 45nm ASIC process our approach results in fewer gates, smaller logic, and reduced power with only a slight increase in latency. We also show that the same weight-shared-with-PASM CNN accelerator can be implemented in resource-constrained FPGAs, where the FPGA has limited numbers of digital signal processor (DSP) units to accelerate the MAC operations.

Convolutional Neural Networks (CNNs) are one of the most successful deep machine learning technologies for processing image, voice and video data. CNNs require large amounts of processing capacity and memory, which can exceed the resources of low power mobile and embedded systems. Several designs for hardware accelerators have been proposed for CNNs which typically contain large numbers of Multiply Accumulate (MAC) units. One approach to reducing data sizes and memory traffic in CNN accelerators is “weight sharing”, where the full range of values in a trained CNN are put in bins and the bin index is stored instead of the original weight value. In this paper we propose a novel MAC circuit that exploits binning in weight-sharing CNNs. Rather than computing the MAC directly we instead count the frequency of each weight and place it in a bin. We then compute the accumulated value in a subsequent multiply phase. This allows hardware multipliers in the MAC circuit to be replaced with adders and selection logic. Experiments show that for the same clock speed our approach results in fewer gates, smaller logic, and reduced power.

CdTe/Si substrates with etch-pit densities ~5 x 10⁴ - 2 x10⁵ cm^-2 and x-ray diffraction full-width at half-maximum 60% of a 3" substrate and ≤85 arcsec over the entire area are now available. Midwave and shortwave HgCdTe infrared detectors fabricated on these substrates have device characteristics as good as those of detectors fabricated on lattice-matched CdZnTe substrates. Also, minority carrier lifetimes of 100s of nanoseconds are measured for CdTe/Si and CdZnTe/Si, and both can be p-doped 10¹⁷ cm^-3 and n-doped >10²⁰ cm^-3. Calculations suggest that the use of these materials should yield multijunction solar cells with efficiencies higher than those of the corresponding III-V multijunction cells at much lower cost, using rugged, large-area, inexpensive active Si substrates. The first CdZnTe/Si single-junction solar cells fabricated by EPIR displayed an electronic-charge times open-circuit voltage, qV_oc, within ~0.45 eV of the CdZnTe bandgap E_g, as good a result as that for the best III-V alloy single-junction cells, and confirmed the suitability of single-crystal CdZnTe/Si for the manufacture of high-efficiency solar cells.

A Woollam M88 spectroscopic ellipsometer was used to characterize the molecular beam epitaxy growth nucleation of Hg_1-xCd_xTe layers on CdZn_0.035Te substrates and the substrate temperature prior to the growth. We developed a new approach to ellipsometry data analysis to better determine the substrate temperature. It is based on the accurate determination of the critical point energies and linewidths, which display strong temperature dependence in the CdZnTe system. The new model was able to resolve temperature differences of the order of +/-2.5^oC. We also show that ellipsometry can be used to characterize the nucleation of Hg_1-xCd_xTe on CdZnTe substrates. More work is in progress to assess the run-to-run reproducibility of our temperature measurement, and to further investigate Hg_1-xCd_xTe nucleation.