Carlos Raiumundo Erig Lima

The parallelism allowed by FPGAs has attracted attention for knowing applications that need processing power. However, the need for specific and very technical development language has not stimulate its broad use. As an alternative, there are High-level Synthesis Languages (HSL), which allow less complicated FPGA use. However, they do not tend to take full advantage of the FPGA technology. Therefore, another alternative was developed, based on the Notification Oriented Paradigm (NOP), called NOP for Digital Hardware (NOP-DH). NOP allows development in high level with its rule-oriented language called NOPL. Its entity decoupling, parallelism, and redundancy avoidance are useful for best performance. In turn, the NOP-DH brings NOP for the FPGA context with the benefits observed in software but enhanced by hardware nature. This paper reviews the NOPL for NOP-DH (NOPL-DH) that aims high level programming for FPGA. The paper proposes the NOPL-DH test by independent developers, by developing a monitoring device for a box transporting bidirectional conveyer. As a result, NOPL-DH allowed high-level development under the NOP-DH structure in an FPGA, without the need for technical knowledge and, still, maintaining and exploring the NOP properties in FPGA

A NILM dataset is a valuable tool in the development of Non-Intrusive Load Monitoring techniques, as it provides a means of evaluation of novel techniques and algorithms, as well as for benchmarking. The figure of merit of a NILM dataset includes characteristics such as the sampling frequency of the voltage, current, or power, the availability of indications (ground-truth) of load events during recording, the variety and representativeness of the loads, and the variety of situations these loads are subject to. Considering such aspects, the proposed LIT-Dataset was designed, populated, evaluated, and made publicly available to support NILM development. Among the distinct features of the LIT-Dataset is the labeling of the load events at sample level resolution and with an accuracy and precision better than 5 ms. The availability of such precise timing information, which also includes the identification of the load and the sort of power event, is an essential requirement both for the evaluation of NILM algorithms and techniques, as well as for the training of NILM systems, particularly those based on Machine Learning.

A multi-agent architecture for a Non-Intrusive Load Monitoring (NILM) solution is presented and evaluated. The underlying rationale for such an architecture is that each agent (load event detection, feature extraction, and classification) outperforms others of the same type in particular scenarios; hence, by combining the expertise of these agents, the system presents an improved performance. Known NILM algorithms, as well as new algorithms, proposed by the authors, were individually evaluated and compared. The proposed architecture considers a NILM system composed of Load Monitoring Modules (LMM) that report to a Center of Operations, required in larger facilities. For the purposed of evaluating and comparing performance, five load event detect agents, five feature extraction agents, and five classification agents were studied so that the best combinations of agents could be implemented in LMMs. To evaluate the proposed system, the COOLL and the LIT-Dataset were used. Performance improvements were detected in all scenarios, with power-ON and power-OFF detection improving up to 13%, while classification accuracy improved up to 9.4%.

This paper proposes an approach for audio preprocessing and noise removal from recordings obtained in natural environments. The method is inspired in the acoustic signature of the audio, and aims to preprocess the recordings of bird songs obtained directly in the field. Using the Spectral Noise Gate technique, the undesired noise is removed on a real application in real time during the recording using an embedded environment. In addition, important statistic features of the audio signal are computed. The main purpose on approach is to eliminate the manual and tedious process of preparing the audio recordings done in the field in order to make them ready to be used as input in other tasks, such as the automatic classification of bird species from recorded bird songs. This is necessary because classification results depend widely from the quality of the input data.

Many real-world engineering problems require high computational power, especially regarding the processing time. Current parallel processing techniques play an important role in reducing the processing time. Recently, reconfigurable computation has gained large attention thanks to its ability to combine hardware performance and software flexibility. Also, the availability of high-density Field Programmable Gate Array devices and corresponding development systems allowed the popularization of reconfigurable computation, encouraging the development of very complex, compact, and powerful systems for custom applications. This work presents an architecture for parallel reconfigurable computation based on the dataflow concept. This architecture allows reconfigurability of the system for many problems and, particularly, for numerical computation. Several experiments were done analyzing the scalability of the architecture, as well as comparing its performance with other approaches. Overall results are relevant and promising. The developed architecture has performance and scalability suited for engineering problems that demand intensive numerical computation.

This work proposes and implements a reconfigurable parallel architecture based on dataflow for numerical computation, named PRADA. This architecture uses concepts of parallel processing to obtain a scalable performance and the dataflow concept for controlling the parallel execution of instructions. PRADA is composed by a control unit and several processing elements (PEs). In the control unit, there are several functional blocks, including data and instruction memories. Each PE is composed by an ALU and buffers. PRADA is organised as a cluster, in which several independent dataflow modules are interconnected together. PRADA was developed in VHDL and implemented in reconfigurable hardware using a FPGA device. Therefore, it can offer high performance, scalability and customised solutions for engineering problems. Results of the application of PRADA to the computation of a digital filter and a cryptography algorithm are presented. Results are also compared with other different architectures, such as microprocessors, ASICs, DSPs, reconfigurable architectures and dataflow architectures. In most cases, PRADA achieved either competitive or higher performance than the other architectures, regarding the measures used. Overall results suggest that this architecture can be applied to several classes of problems that may require a high throughput, such as cryptography, optimisation and scientific computing.

The emCGA is a new extension of the compact genetic algorithm (CGA) that includes elitism and a mutation operator. These improvements do not increase significantly the computational cost or the memory consumption and, on the other hand, increase the overall performance in comparison with other similar works. The emCGA is applied to the problem of object recognition in digital images. The objective is to find a reference image (template) in a landscape image, subject to distortions and degradation in quality. Two models for dealing with the images are proposed, both based on the intensity of light. Several experiments were done with reference and landscape images, under different situations. The emCGA was compared with an exhaustive search algorithm and another CGA proposed in the literature. The emCGA was found to be more efficient for this problem, when compared with the other algorithms. We also compared the two proposed models for the object. One of them is more suitable for images with rich details, and the other for images with low illumination level. Both models seem to perform equally in the presence of distortions. Overall, results suggested the efficiency of emCGA for template matching in images and encourages future developments.

The amount of data produced by the several genomic sequencing projects has increased dramatically in recent years. One of the main goals of bioinformatics is to analyze biological data aiming at identifying genes. The splice junction recognition problem is an important part of the gene detection problem. This work evaluates the performance of two classification models, derived from the weight matrix model, when applied to the splice junction recognition problem. Two splice junction data sets were used in this work and some measures of predictive accuracy were reported. Based on the experiments, classification thresholds were established, which can be useful for further implementation of an automatic gene detection system.

This paper presents a comparison between two technologies for reconfigurable circuits: FPGA's and FPAA's. The comparison is based on a case study of the area of industrial control using simulations with both types of reconfigurable devices. Several design issues are discussed, including the ease of implementation, accuracy, capacity, consumption and size, among others. Based on the case study, we present qualitative directions to choose the most suitable reconfigurable device for similar applications.