Dorian Amiet

Quantitative fluorescence microscopy requires photon-efficiency, speed and accurate intensity and lifetime measurements. Time-correlated single-photon counting (TCSPC) simultaneously captures intensity and lifetime, but photon pile-up distorts both signals at high count rates, preventing fast acquisitions. Existing corrections discard photons, distort intensity, or require specialized detectors. Here we introduce PURELIGHT, an integrated hardware and software framework that simultaneously recovers undistorted intensities and lifetimes at count rates far beyond conventional pile-up limits. PURELIGHT works with hybrid photodetectors, silicon photomultipliers and photomultiplier tubes while retaining over three times more photons than alternative approaches. Using two-photon imaging, we showcase PURELIGHT’s superior accuracy and spatial contrast, demonstrating video-rate subcellular lifetime imaging in awake mice, a unique lifetime-calibrated ratiometric modality and crosstalk-free temporal multiplexing. By removing the limits that have confined TCSPC to low-signal applications, PURELIGHT promotes the adoption of quantitative, photon-efficient microscopy across the life sciences.

Two-photon excited fluorescence microscopy (2PM) has revolutionized neuroscience, allowing the investigation of biological dynamics with subcellular and subsecond resolution in living animals.^1,2 Fluorescent labeling with proteins and dyes has been used to elucidate the morphology and behavior of cells and blood vessels under physiological and pathological conditions, whereas functional readouts such as calcium imaging or blood flow measurements have shed light on dynamic phenomena such as neuronal activity and neurovascular coupling.^3,4 However, despite its successes, intensity-based 2PM is heavily affected by confounding factors such as fluorophore expression, tissue scattering and absorption, and sample motion. Although these problems can be somewhat alleviated using ratiometric approaches, the wavelength dependence of scattering and absorption still prevents accurate quantitation. Thus, traditional 2PM is insufficient to investigate biological processes such as metabolism, which require the precise quantification of molecule concentrations.^5,6

Intensity-based two-photon microscopy (2PM) is a cornerstone of biomedical research but lacks the ability to measure concentrations, a pivotal task for longitudinal studies and quantitative comparisons. Fluorescence Lifetime Imaging (FLIM) based on Time-Correlated Single Photon Counting (TCSPC) can overcome those limits but suffers from “pile-up” distortions at high photon count rates, severely limiting acquisition speed. We introduce the “laser period blind time” (LPBT) method to correct pile-up distortions in photon counting electronics, enabling reliable low-cost TCSPC-FLIM at high count rates. The correction was implemented on low-cost hardware based on a field programable gate array (FPGA) and validated using a combination of in silico simulations and in vitro, ex vivo and in vivo measurements. The LBPT approach achieves <3% error in lifetime measurements at count rates more than ten times higher than traditional limits, allowing robust FLIM imaging of sub-second metabolite dynamics with subcellular resolution. Our work enables high-precision, cost-effective FLIM imaging at rates comparable to commercial systems and at a fraction of the cost, facilitating the adoption of FLIM across all areas of research needing affordable, quantitative live imaging solutions.

Cryptographic algorithms are indispensable from today’s world and often require high-throughput implementations accelerated by specialized hardware like field programmable gate arrays (FPGAs). However, these implementations are vulnerable to side-channel attacks such as clock glitch attacks. This paper presents a clock glitch generator designed to insert glitches into a clock signal using only FPGA clocking resources to ensure signal purity. By incorporating an FPGA-internal calibration method, the start and width of the glitches can be set with a precision of 0.53°, equal to 14.8 ps, for a 100 MHz clock. The generator’s architecture allows glitches to be inserted in the positive and the negative phase of the clock. This increases the versatility of the possible attacks. The clock glitch generator was used to attack both the mixed-mode clock manager (MMCM) and phase-locked loop (PLL) primitives within the 7-Series and Ultrascale+ family. Despite the PLL’s ability to filter out clock glitches, an attack scenario was successfully identified that stealthily increased the output frequency of a 7-Series MMCM and PLL by up to 68%.

In recent years, a substantial amount of research has been conducted and progress made in the area of quantum computers. Small functional prototypes have already been reported. If they scale as expected, they will eventually be able to break current public-key cryptosystems. The goal of post-quantum cryptography is to develop cryptographic systems that are secure against attacks originating from both quantum and classical computers. Frequently referred post-quantum signature schemes are based on the security of hash functions. A promising candidate in this group is SPHINCS-256. This paper presents the first FPGA-based hardware accelerator for SPHINCS-256. It can be implemented on an entry-level FPGA, occupying roughly 19,000 LUTs, 38,000 FFs and 36 BRAMs. On a Kintex-7 Xilinx FPGA, signing takes 1.53 milliseconds, and verification needs only 65 microseconds. Area and throughput of the accelerator are in a range that outperform today’s widely used RSA signature scheme. The performance can even keep up with ECDSA accelerators. Hence, SPHINCS-256 is a hot candidate to replace RSA and ECDSA in a post-quantum world.

Elliptic curve cryptography (ECC) is widely used as an efficient mechanism to secure private data using public-key protocols. This paper focuses on ECC over prime fields (GF(p)). We present a novel hardware architecture that calculates the elliptic curve point multiplication (ECPM). Our processor supports arbitrary prime fields with sizes up to 1024 bits. Different standards, which use curves in short Weierstrass form are supported. A Xilinx Virtex-7 implementation of the proposed hardware architecture takes from 0.69 ms for a 192-bit point multiplication up to 9.7 ms for 512-bit. The implementation takes only 20 DSP slices and 6816 LUTs. To the authors knowledge, this is the best performance reported so far for ECC point multiplication for arbitrary prime field curves without the use of FPGA reconfiguration.