Abdel Martinez Alonso

This article describes the design and performance analysis of a charge domain mixed-signal multiply-accumulator (MAC) using RDAC, CDAC, and SAR-ADC with an 8-bit resolution for input, weight, and output. The arithmetic accuracy is mainly determined by the ADC, and the gain error has a significant impact. The mismatches and thermal noises of the RDAC and the CDAC are averaged by the number of multiply-accumulate units m connected to one ADC. As a result, if m is large enough, mismatches and thermal noises have a limited impact on the computation accuracy. Most of the computational energy is determined by the energy consumed by the SAR-ADC, and the computational energy per operation can be reduced by increasing m. This last metric is mainly determined by the charge and discharge energy of the CDAC for sufficiently large m values. Furthermore, since RDAC consumes energy unnecessarily, the turn-off timing of RDAC should be optimized. These MAC units have been designed and prototyped using 28 nm CMOS technology, integrating 12,288 arithmetic units while operating at 180 MHz, resulting in an arithmetic speed of 4.4 TOPS. The r-MVM accuracy is about 1% and a high energy efficiency of 240 TOPS/W as a MAC macro and 64.4 TOPS/W as a system has been achieved.

This paper describes a digital-mapping direct digital frequency synthesizer having a tuning and amplitude resolutions of 24 and 10 bits, respectively. This Si-CMOS-monolithic microwave-integrated circuit (MMIC) is the first solution supporting a sampling rate of 7 GS/s with frequency modulation, phase modulation (PM), and amplitude modulation (AM) in the digital domain. It includes a 14 bits pipelined ripple-carry phase adder and a 10-bits high-speed amplitude multiplier. The minimum frequency, phase, and amplitude steps are 417.2 Hz, 0.022°, and 1.17 mV, respectively. A proof-of-concept chip with an active area of 0.23 mm2 was fabricated in a 1P9M 65-nm CMOS process and characterized in low-profile quad flat package (LQFP). The worst case wideband/narrowband spurious-free dynamic range is 32/42 dBc. This system consumes 85.9 mW/(GS/s) from a 1.2-V power supply when the PM/AM are enabled, resulting in an figure of merit (FoM) of 469.6 GS/s · 2(SFDR/6)/W. The absolute single sideband phase noise at 100 KHz offset from the carrier was better than -125 dBc/Hz in all the evaluated frequencies. A latency of 12.86 ns was measured when operating at 7 GS/s.

A 7GS/s complete-DDFS-solution featuring a two-times interleaved RDAC with 1.2Vpp-diff output swing was fabricated in 65nm CMOS. The frequency tuning and amplitude resolutions are 24-bits and 10-bits respectively. The RDAC includes a mixed-signal, high-speed architecture for random swapping thermometer coding dynamic element matching that improves the narrowband SFDR up to 8dB for output frequencies below 1.85GHz. The proposed techniques enable a 7 GS/s operation with a spurious-free dynamic range better than 32dBc over the full Nyquist bandwidth. The worst case narrowband SFDR is 42dBc. This system consumes 87.9mW/(GS/s) from a 1.2V power supply when the RSTC-DEM method is enabled, resulting in a FoM of 458.9GS/s . 2((SFDR/6))/W. A proof-of-concept chip with an active area of only 0.22mm(2) was measured in prototypes encapsulated in a 144-pins low profile quad flat package.

This paper describes a digital-mapping DDFS with a frequency tuning and amplitude resolutions of 24-bits and 10-bits respectively. This Si-CMOS-MMIC is the first solution supporting a sampling rate of 7GS/s and frequency, phase and amplitude modulations in the digital domain. It includes a 14-bits pipelined ripple-carry adder and a 10-bits high-speed multiplier for phase and amplitude modulations respectively. The worst case wideband/narrowband SFDR is 32dBc/42dBc. This system consumes 85.9mW/(GS/s) from a 1.2V power supply when the amplitude/phase modulations are enabled, resulting in a FoM of 469.6GS/s-2^(SFDR/6)/W. A proof-of-concept chip with an active area of 0.23mm² was characterized in LQFP packages.

A 7GS/s DDFS MMIC featuring a Two-Times Interleaved RDAC with 1.2Vpp-diff output swing was fabricated in 65nm CMOS. The frequency tuning and amplitude resolutions are 24-bits and 10-bits respectively. The RDAC includes a mixed-signal, high-speed architecture for Random Swapping Thermometer Coding Dynamic Element Matching that improves the narrowband SFDR up to 8dB for output frequencies below 1.85GHz. The worst case wideband/narrowband SFDR is 32dBc/42dBc. This system consumes 87.9mW/(GS/s) from a 1.2V power supply when the RSTC-DEM method is enabled, resulting in a FoM of 458.9GS/s-2^(SFDR/6)/W. A Proof-of-Concept chip with an active area of only 0.22mm² was measured in LQFP packages.

This paper introduces a novel Direct Digital Frequency Synthesizer (DDFS) based on Complementary Dual-Phase Latch-Based digital design. Compared to conventional DDFS using Flip-Flop as synchronizing element, the proposed approach allows to double the sampling data rate while enhancing the clock skew tolerance and system latency. The design features a 24 bits pipelined Phase Accumulator (PA) and a 14×10 bits Phase to Amplitude Converter (PAC). The Phase to Amplitude Converter module is compressed using Quarter Wave Symmetry technique and is entirely made up of combinational logic inserted into 12 Complementary Dual-Phase Latch-Based pipeline stages. The logic is represented in the form of Sum of Product (SoP) terms obtained from a 14×10 bits sinusoidal Look-Up-Table. The proposed DDFS is designed and simulated based on TSMC 65nm CMOS standard-cell technology. A maximum data sampling rate of 6.8 GS/s and 0.022 W/ GS/s Power Efficiency (PE) is expected.

Worldwide, the technological change of Analog Television into Terrestrial Digital Television started since 1998. It's an inevitable change that each country has to face and which is part of the digitizing process that already has taken place in many other technologies. In order to determine the most convenient standard for Cuba, and technological infrastructure planning, it was necessary to take into account several aspects, particular technological issues. This paper comprises the evaluation of reception quality parameters for DTMB digital television signal broadcasting standard, with 6MHz bandwidth. DTMB has been adopted after more than ten years of work conducted by a Technical Committee created with this purpose. All the experiments have been carried out according to the UIT-R BT.2035-2 report: “Guidelines and techniques for the evaluation of digital terrestrial television broadcasting systems including assessment of their coverage areas”. The objective of Digital Terrestrial Television Broadcasting (DTTB) testing and trials is to evaluate the performance of an available system in a variety of transmission configurations and reception conditions. These tests include measurements of receiver performance in the presence of Random Noise, RF signal level Variation (Dynamic Range) and Static Multipath Interference.