Madhushankara Maila
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Madhushankara Maila has a total of 32 co-authors. Here are the top co-authors by number of shared publications:
- H. Muralikrishna
Manipal Institute of Technology, Manipal Academy of Higher Education, Manipal, India
4 shared publications - Ribu Mathew
Manipal Academy of Higher Education
4 shared publications - Suchitra Shenoy
Manipal School of Information Sciences, Manipal Academy of Higher Education, Manipal, India
4 shared publications Keerthana Prasad
3 shared publicationsPrashanth Kumar Shetty
Manipal Academy of Higher Education
3 shared publications- Aneesha Acharya K.
Department of Instrumentation and Control Engineering, Manipal Institute of Technology, Manipal Academy of Higher Education (MAHE), Manipal, India
2 shared publications
Latest Publications
- Open Access
- 15 October 2026
- Published by Springer Nature in Discover Applied Sciences
Deterministic fixed point inference with tiled parallelism for ASIC implementation of human activity recognition
Deploying machine learning models on hardware platforms requires careful handling of numerical precision, limited resources, and predictable execution. In practice, mismatches between floating-point software models and their register-transfer level (RTL) implementations can lead to inconsistent inference results. In this proposed work, a hardware–software co-designed methodology that ensures bit-accurate and deterministic inference across floating-point and RTL implementations is proposed. A fully connected neural network with a 64–64–6 architecture is trained on the UCI human activity recognition (HAR) dataset and mapped to a hardware-friendly fixed-point representation. An application specific integrated circuit (ASIC)-oriented RTL design is developed and validated against a cycle-accurate Python fixed-point model to ensure consistency between software and hardware execution. To improve the performance, a tiled parallel multiply–accumulate (MAC) architecture with $$\textit{PAR}=8$$ is employed, enabling higher throughput without significantly increasing hardware complexity. The model achieves $$93.24\%$$ accuracy in floating-point and $$92.66\%$$ after fixed-point and RTL implementation, with a reduction of 0.58 percentage points following quantization. The RTL outputs match the fixed-point model across all evaluated samples, confirming its deterministic behavior. Synthesis using the TSMC 12 nm technology achieves a compute energy of 30.33 pJ per inference and a total inference energy of 170.67 pJ, demonstrating the suitability of the proposed methodology for edge AI applications.- 15 October 2026
- Published by Springer Nature in Discover Applied Sciences
Open AccessDeterministic fixed point inference with tiled parallelism for ASIC implementation of human activity recognition
Deploying machine learning models on hardware platforms requires careful handling of numerical precision, limited resources, and predictable execution. In practice, mismatches between floating-point software models and their register-transfer level (RTL) implementations can lead to inconsistent inference results. In this proposed work, a hardware–software co-designed methodology that ensures bit-accurate and deterministic inference across floating-point and RTL implementations is proposed. A fully connected neural network with a 64–64–6 architecture is trained on the UCI human activity recognition (HAR) dataset and mapped to a hardware-friendly fixed-point representation. An application specific integrated circuit (ASIC)-oriented RTL design is developed and validated against a cycle-accurate Python fixed-point model to ensure consistency between software and hardware execution. To improve the performance, a tiled parallel multiply–accumulate (MAC) architecture with $$\textit{PAR}=8$$ is employed, enabling higher throughput without significantly increasing hardware complexity. The model achieves $$93.24\%$$ accuracy in floating-point and $$92.66\%$$ after fixed-point and RTL implementation, with a reduction of 0.58 percentage points following quantization. The RTL outputs match the fixed-point model across all evaluated samples, confirming its deterministic behavior. Synthesis using the TSMC 12 nm technology achieves a compute energy of 30.33 pJ per inference and a total inference energy of 170.67 pJ, demonstrating the suitability of the proposed methodology for edge AI applications. - Open Access
- 14 January 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Access
- Vol. 14, 10473-10483
Toward Low-Resource Hydroacoustic Signature-Based Ship Detection With Out-of-Domain Detection Capability
Hydroacoustic signature-based ship detection (HSD) involves identifying and classifying vessels by analyzing the underwater sound patterns they emit, including propeller noise, engine vibrations, and hull flow disturbances. This technique is useful in naval surveillance, anti-submarine warfare, maritime traffic monitoring, and underwater environmental studies where visual or radar detection is limited. Since HSD is independent of visibility conditions and covert due to its passiveness, it can be used as a complementary modality along with traditional ship detection methods. However, machine-learning based automatic HSD is sensitive to factors like variability in ocean acoustic environments, background noise, similarity of signatures among different classes of ships, etc., especially in low-resource conditions where there is lack of sufficient training data to train a generalized HSD model. Furthermore, out-of-domain (OOD) detection is necessary for reliable surveillance in real-world applications. Motivated by all these, in this paper, we present different methods to improve the performance of low-resource HSD with OOD detection capability. Specifically, we first propose to use pre-trained PaSST and EAT models for efficient feature extraction for low-resource HSD. Since different encoder layers of these pre-trained models encode the input differently, a detailed layer-wise analysis of the performance is conducted on both models to select the optimum layer for HSD-specific feature extraction. Following this, we incorporate OOD detection capability to the HSD model using GMM-based, K Nearest Neighbor (KNN) based and OpenMax-based thresholding approaches. The results obtained on a publicly available dataset indicate that the HSD model trained using PaSST features, when coupled with the GMM-based OOD detector achieves the best performance, with an AUROC of around 93% and an accuracy score of nearly 86%.
- 14 January 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Access
- Vol. 14, 10473-10483
Open AccessToward Low-Resource Hydroacoustic Signature-Based Ship Detection With Out-of-Domain Detection Capability
Hydroacoustic signature-based ship detection (HSD) involves identifying and classifying vessels by analyzing the underwater sound patterns they emit, including propeller noise, engine vibrations, and hull flow disturbances. This technique is useful in naval surveillance, anti-submarine warfare, maritime traffic monitoring, and underwater environmental studies where visual or radar detection is limited. Since HSD is independent of visibility conditions and covert due to its passiveness, it can be used as a complementary modality along with traditional ship detection methods. However, machine-learning based automatic HSD is sensitive to factors like variability in ocean acoustic environments, background noise, similarity of signatures among different classes of ships, etc., especially in low-resource conditions where there is lack of sufficient training data to train a generalized HSD model. Furthermore, out-of-domain (OOD) detection is necessary for reliable surveillance in real-world applications. Motivated by all these, in this paper, we present different methods to improve the performance of low-resource HSD with OOD detection capability. Specifically, we first propose to use pre-trained PaSST and EAT models for efficient feature extraction for low-resource HSD. Since different encoder layers of these pre-trained models encode the input differently, a detailed layer-wise analysis of the performance is conducted on both models to select the optimum layer for HSD-specific feature extraction. Following this, we incorporate OOD detection capability to the HSD model using GMM-based, K Nearest Neighbor (KNN) based and OpenMax-based thresholding approaches. The results obtained on a publicly available dataset indicate that the HSD model trained using PaSST features, when coupled with the GMM-based OOD detector achieves the best performance, with an AUROC of around 93% and an accuracy score of nearly 86%.
- 2 January 2026
- Published by Springer Nature
- p. 13-21
Delay and Power Analysis of ALU with 180, 90, and 45 nm Technologies
- 2 January 2026
- Published by Springer Nature
- p. 13-21
Delay and Power Analysis of ALU with 180, 90, and 45 nm Technologies
- Open Access
- 1 January 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Access
- Vol. 14, 160246-160257
Cross-Layer RTL Fault Detection Using Temporal Deviation, Leakage-Aware Switching-Activity Monitoring, and EV-Specific Safety Constraints
- 1 January 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Access
- Vol. 14, 160246-160257
Open AccessCross-Layer RTL Fault Detection Using Temporal Deviation, Leakage-Aware Switching-Activity Monitoring, and EV-Specific Safety Constraints
- Open Access
- 20 December 2025
- Published by Springer Nature in International Journal of Information Technology
- p. 1-14
Exploring layer-wise features of whisper and wav2vec 2.0 models and their aggregation for infant cry classification in low-resource conditions
Infants use cry as their primary mode of communication, which they use to signal hunger, discomfort, illness etc., to their caregivers. Understanding and interpreting these cries can provide critical insights into their well-being and aid in timely intervention. However, manual analysis of infant cry is subjective and prone to variability, especially when parents/caregivers have limited experience. While deep learning (DL) based infant cry classification (ICC) systems can be handy in such situations, they need large datasets to train robust models, without which they become vulnerable to challenges like variability in cry patterns across infants, noise in real-world recordings, etc. One way to improve the performance in such low-resource conditions is to use transfer-learning, where features extracted from pre-trained model are used to build models for the task-at-hand. Motivated by this, we propose to build ICC system using features from pre-trained wav2vec 2.0 and whisper models and compare their performance with the traditional ICC system that uses MFCC features. Since different layers of wav2vec 2.0 and whisper might encode the required information differently, we first empirically determine their relevance to ICC. In order to best utilize the complementary information that may be present in the features extracted from different layers and time-steps, we then propose to fuse them together. We propose to use different fusion strategies such as statistical pooling, attentive statistical pooling, linear-merge and attention-merge based approaches to aggregate the features. Furthermore, we explore different deep-learning architectures such as LSTM and x-vector-based architecture to perform cry classification. Obtained results indicate that attention-merge on wav2vec 2.0 large features combined with x-vector gives the best performance.
- 20 December 2025
- Published by Springer Nature in International Journal of Information Technology
- p. 1-14
Open AccessExploring layer-wise features of whisper and wav2vec 2.0 models and their aggregation for infant cry classification in low-resource conditions
Infants use cry as their primary mode of communication, which they use to signal hunger, discomfort, illness etc., to their caregivers. Understanding and interpreting these cries can provide critical insights into their well-being and aid in timely intervention. However, manual analysis of infant cry is subjective and prone to variability, especially when parents/caregivers have limited experience. While deep learning (DL) based infant cry classification (ICC) systems can be handy in such situations, they need large datasets to train robust models, without which they become vulnerable to challenges like variability in cry patterns across infants, noise in real-world recordings, etc. One way to improve the performance in such low-resource conditions is to use transfer-learning, where features extracted from pre-trained model are used to build models for the task-at-hand. Motivated by this, we propose to build ICC system using features from pre-trained wav2vec 2.0 and whisper models and compare their performance with the traditional ICC system that uses MFCC features. Since different layers of wav2vec 2.0 and whisper might encode the required information differently, we first empirically determine their relevance to ICC. In order to best utilize the complementary information that may be present in the features extracted from different layers and time-steps, we then propose to fuse them together. We propose to use different fusion strategies such as statistical pooling, attentive statistical pooling, linear-merge and attention-merge based approaches to aggregate the features. Furthermore, we explore different deep-learning architectures such as LSTM and x-vector-based architecture to perform cry classification. Obtained results indicate that attention-merge on wav2vec 2.0 large features combined with x-vector gives the best performance.
- Open Access
- 4 September 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Access
- Vol. 13, 161016-161025
Speech Enhancement for Electrolarynx Devices Using M-RLS: Intelligibility Improvement and Low-Power Hardware Feasibility
An electrolarynx, a widely used assistive device for voice restoration for individuals with laryngeal impairments, often suffers from mechanical buzz and poor intelligibility, limiting its everyday applicability. This work presents a modified recursive least squares (M-RLS) algorithm specifically designed to enhance electrolarynx speech by attenuating the excitation noise characteristic while preserving speech quality. The proposed work is evaluated on data across 44 speech samples and benchmarked against a baseline method using three objective metrics: the perceptual evaluation of speech quality (PESQ), short-time objective intelligibility (STOI), and the signal-to-noise ratio (SNR). The proposed M-RLS approach demonstrated notable improvements, with PESQ scores reaching 3.01, a median STOI value of 0.7, and an SNR performance comparable to that of the baseline. In addition, to evaluate its feasibility in embedded systems, the algorithm was synthesized in 15 nm technology to form an application-specific integrated circuit (ASIC), confirming its suitability for real-time, low-power speech enhancement applications. The design occupies 0.289 mm², operates at 1 GHz, and consumes only 16.9 mW, yielding a power-delay product of 15.41 pJ, making it well suited for energy-constrained environments such as electrolarynx-based speech enhancement systems. The proposed method is also quick prototyped via a DE10 field programmable gate array (FPGA) with a maximum operating frequency of 253.8 MHz.
- 4 September 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Access
- Vol. 13, 161016-161025
Open AccessSpeech Enhancement for Electrolarynx Devices Using M-RLS: Intelligibility Improvement and Low-Power Hardware Feasibility
An electrolarynx, a widely used assistive device for voice restoration for individuals with laryngeal impairments, often suffers from mechanical buzz and poor intelligibility, limiting its everyday applicability. This work presents a modified recursive least squares (M-RLS) algorithm specifically designed to enhance electrolarynx speech by attenuating the excitation noise characteristic while preserving speech quality. The proposed work is evaluated on data across 44 speech samples and benchmarked against a baseline method using three objective metrics: the perceptual evaluation of speech quality (PESQ), short-time objective intelligibility (STOI), and the signal-to-noise ratio (SNR). The proposed M-RLS approach demonstrated notable improvements, with PESQ scores reaching 3.01, a median STOI value of 0.7, and an SNR performance comparable to that of the baseline. In addition, to evaluate its feasibility in embedded systems, the algorithm was synthesized in 15 nm technology to form an application-specific integrated circuit (ASIC), confirming its suitability for real-time, low-power speech enhancement applications. The design occupies 0.289 mm², operates at 1 GHz, and consumes only 16.9 mW, yielding a power-delay product of 15.41 pJ, making it well suited for energy-constrained environments such as electrolarynx-based speech enhancement systems. The proposed method is also quick prototyped via a DE10 field programmable gate array (FPGA) with a maximum operating frequency of 253.8 MHz.
- 12 August 2025
- Published by Springer Nature
- p. 223-233
Verification of DDR4 SDRAM Using SystemVerilog
- 21 May 2025
- Published by Springer Nature in Analog Integrated Circuits and Signal Processing
- Vol. 124 (1) , 1-13
Seamless connectivity: universal asynchronous receiver and transmitter for implantable medical devices
- 21 May 2025
- Published by Springer Nature in Analog Integrated Circuits and Signal Processing
- Vol. 124 (1) , 1-13
Seamless connectivity: universal asynchronous receiver and transmitter for implantable medical devices
- 30 April 2025
- Published by World Scientific Pub Co Pte Ltd in Journal of Circuits, Systems and Computers
- Vol. 34 (12)
Design, Verification and Hardware Implementation of 4kB Synchronous FIFO for Automatic Vehicle Communication Applications
Sustainability in in-vehicle communication comprises the integration of wireless technology for faster and more reliable connectivity. Driverless vehicles need to schedule various tasks on a priority basis. The first-in-first-out (FIFO) data structure is critical for handling sensor data and communication information, and a memory queue is important for controlling data flow through organized read and write processes. This study focuses on the design, verification and synthesis of a FIFO with a size of 4k bytes. By operating on a single clock signal, synchronous FIFO enables smooth data transmission between a source and destination within the same clock domain. The designed FIFO resulted in an area of 41.401[ ]mm2, a power dissipation of 0.506[ ]mW and a critical path delay of 0.03[ ]ps when a 15[ ]nm open-cell library from Nangate was used. The design is also implemented using an Arria II field programmable gate array (FPGA), which results in a maximum clock frequency of 33.33[ ]GHz.
- 30 April 2025
- Published by World Scientific Pub Co Pte Ltd in Journal of Circuits, Systems and Computers
- Vol. 34 (12)
Design, Verification and Hardware Implementation of 4kB Synchronous FIFO for Automatic Vehicle Communication Applications
Sustainability in in-vehicle communication comprises the integration of wireless technology for faster and more reliable connectivity. Driverless vehicles need to schedule various tasks on a priority basis. The first-in-first-out (FIFO) data structure is critical for handling sensor data and communication information, and a memory queue is important for controlling data flow through organized read and write processes. This study focuses on the design, verification and synthesis of a FIFO with a size of 4k bytes. By operating on a single clock signal, synchronous FIFO enables smooth data transmission between a source and destination within the same clock domain. The designed FIFO resulted in an area of 41.401[ ]mm2, a power dissipation of 0.506[ ]mW and a critical path delay of 0.03[ ]ps when a 15[ ]nm open-cell library from Nangate was used. The design is also implemented using an Arria II field programmable gate array (FPGA), which results in a maximum clock frequency of 33.33[ ]GHz.
- 29 October 2024
- Published by Springer Nature
- p. 409-419
Machine Learning-Based Power Analysis of RISC-V Processor
- 29 October 2024
- Published by Springer Nature
- p. 409-419
Machine Learning-Based Power Analysis of RISC-V Processor