Mariusz Naumowicz

This article presents a comparative analysis of two types of generators of random sequences: one based on a discrete chaotic system being the logistic map, and the other being a commercial quantum random number generator QUANTIS-USB-4M. The results of the conducted analysis serve as a guide for selecting the type of generator that is more suited for a specific IoT solution, depending on the functional profile of the target application and the amount of random data required in the cryptographic process. This article discusses both the theoretical foundations of chaotic phenomena underlying the pseudorandom number generator based on the logistic map, as well as the theoretical principles of photon detection used in the quantum random number generators. A hardware IP Core implementing the logistic map was developed, suitable for direct implementation either as a standalone ASIC using the SkyWater PDK process or on an FPGA. The generated bitstreams from the implemented IP Core were evaluated for randomness. The analysis of the entropy levels and evaluation of randomness for both the logistic map and the quantum random number generator were performed using the ent tool and NIST test suite.

This paper presents a prototype wearable Cryptographically Secure PseudoRandom Bit Generator CSPRBG (wearable CSPRBG). A vest prototype has been fabricated to which an evaluation board with a ZYBO (ZYnq BOard) Zynq Z-7010 has been mounted using tailoring technology. In this system, a seed generator and block cryptographic algorithms responsible for the generation of pseudo-random values were implemented. A microphone and an accelerometer recorded sound and acceleration during the use of the prototype vest, and these recordings were passed to the seed generator and used as entropy sources. Hardware implementations were made for several selected Block Cryptographic algorithms such as Advanced Encryption Standard (AES), Twofish and 3DES. The random binary values generated by the wearable CSPRBG were analyzed by National Institute of Standards and Technology (NIST) statistical tests as well as ENT tests to evaluate their randomness, depending on the configuration of the entropy sources used. The idea of possible development of the wearable CSPRBG as a System on Chip (SoC) solution is also presented.

This paper presents a system for the remote design and testing of electronic circuits and devices with FPGAs during COVID-19 and similar lockdown periods when physical access to laboratories is not permitted. The system is based on the application of the IoT concept, in which the final device is a test board with an FPGA chip. The system allows for remote visual inspection of the board and the devices linked to it in the laboratory. The system was developed for remote learning taking place during the lockdown periods at Poznan University of Technology (PUT) in Poland. The functionality of the system is confirmed by two demonstration tasks (the use of the temperature and humidity DHT11 sensor and the design of a generator of sinusoidal waveforms) for students in the fundamentals of digital design and synthesis courses. The proposed solution allows, in part, to bypass the time-consuming simulations, and accelerate the process of prototyping digital circuits by remotely accessing the infrastructure of the microelectronics laboratory.

Edge computing (processing data close to its source) is one of the fastest developing areas of modern electronics and hardware information technology. This paper presents the implementation process of an analog CMOS preprocessor for use in a distributed environment for processing medical data close to the source. The task of the circuit is to analyze signals of vesicle fusion, which is the basis of life processes in multicellular organisms. The functionality of the preprocessor is based on a classifier of full and partial fusions. The preprocessor is dedicated to operate in amperometric systems, and the analyzed signals are data from carbon nanotube electrodes. The accuracy of the classifier is at the level of 93.67%. The implementation was performed in the 65 nm CMOS technology with a 0.3 V power supply. The circuit operates in the weak-inversion mode and is dedicated to be powered by thermal cells of the human energy harvesting class. The maximum power consumption of the circuit equals 416 nW, which makes it possible to use it as an implantable chip. The results can be used, among others, in the diagnosis of precancerous conditions.

The paper presents a method of optimizing frequency characteristics of filter banks in terms of their implementation in digital CMOS technologies in nanoscale. Usability of such filters is demonstrated by frequency-interleaved (FI) analog-to-digital converters (ADC). An analysis filter present in these converters was designed in switched-current technique. However, due to huge technological pitch of standard digital CMOS process in nanoscale, its characteristics substantially deviate from the required ones. NANO-studio environment presented in the paper allows adjustment, with transistor channel sizes as optimization parameters. The same environment is used at designing a digital synthesis filter, whereas optimization parameters are input and output conductances, gyration transconductances and capacitances of a prototype circuit. Transition between analog s and digital z domains is done by means of bilinear transformation. Assuming a lossless gyrator-capacitor (gC) multiport network as a prototype circuit, both for analysis and synthesis filter banks in FI ADC, is an implementation of the strategy to design filters with low sensitivity to parameter changes. An additional advantage is designing the synthesis filter as stable infinite impulse response (IIR) instead of commonly used finite impulse response (FIR) filters. It provides several dozen-fold saving in the number of applied multipliers.. The analysis and synthesis filters in FI ADC are implemented as filter pairs. An additional example of three-filter bank demonstrates versatility of NANO-studio software.

The article presents implementation details of a Sigma-Delta modulator for use in ADC converters of signals with a really low amperage, i.e. up to 1 nA. The paper describes an adaptation of the moderate-inversion technique for processing biomedical signals obtained using amperometric measurements or measurements of living organisms. The analog part of the circuit operates in current mode. The modulator structure is based on a current-to-frequency converter and was designed using the classic digital 65 nm CMOS technology. The paper presents results obtained using post-layout simulations of the modulator. The modulator is able to process frequencies up to 10 kHz and is sampled with a 10 MHz frequency. SNDR was obtained at the level of 55.1 dB and SNR equaling 58.2 dB. The input impedance of the presented AFE occurs at 1 GQ. The power consumption of the whole circuit equals 276 nW and the circuit occupies 0.00442 mm2 of area, which also makes it suitable for implantable-chip applications. The paper is concluded with analyses of sensitivity of the circuit.