Ji Shu

We present a GaN-HEMT/SiC-JFET cascode device that replaces the most performance-and reliability-limiting low-mobility MOS channel of SiC MOSFETs with a high-quality GaN 2-D-electron-gas (2DEG) channel. Compared with SiC MOSFETs, the p-GaN gate-stack of the GaN/SiC cascode device delivers much lower gate charge Q_G, thermally stable threshold voltage V_TH, smaller specific ON-resistance R_ON.SP, and faster switching speed with substantially lower switching loss. A compact 3-D co-packaging solution with stacked GaN and SiC chips results in greatly reduced parasitic interconnection inductance (L_P), thereby suppressing the switching delay and switching loss. More importantly, the ultralow L_P is shown to play a critical role in reclaiming the dv/dt controllability, which has long been a prevalent issue for cascode devices that make them vulnerable to electromagnetic interference (EMI) issues. With an ultralow L_P, an increased capacitive gate-to-drain coupling (i.e., C_GD) in the low-voltage gate control GaN HEMT would allow strong dv/dt control via changing the external gate resistance R_G in the gate driver circuit, which is the most simple and user-friendly control method in applications. The demonstrated GaN/SiC cascode device unveils an ultimate power device that unlocks the full potential of wide bandgap (WBG) semiconductors.

To unlock the full fast-switching potential of the GaN-HEMT/SiC-JFET cascode device, parasitic interconnection inductances are minimized with a 3-D stacked co-packaging configuration. This configuration offers the benefits of reduced switching loss and suppressed oscillation. Equipped with the 3-D co-package configuration, the dv/dt control capability of the GaN/SiC cascode device is enhanced by introducing an additional gate-drain capacitor, C_GD-LV, to the low-voltage GaN HEMT. This additional C_GD-LV improves the coupling between the input control gate voltage and the JFET's gate voltage, which ultimately determines the switching speed of the GaN/SiC cascode device. Experimental results verified the GaN/SiC cascode device, when equipped with the 3-D co-packaged configuration and the additional C_GD-LV, demonstrated fast switching capability with adequate dv/dt control.

A gallium nitride (GaN) two-stage comparator based on complementary logic (CL) architecture is demonstrated and systematically investigated. The comparator features monolithically integrated enhancement-mode n-channel and p-channel GaN field-effect transistors on a commercial p-GaN gate high-electron-mobility transistor (HEMT) platform. Benefiting from energy-efficient CL configuration, the two-stage comparator exhibits rail-to-rail operation from 25 °C to 200 °C with reduced power consumption. The temperature-dependent voltage transfer characteristics, output waveforms, and frequency responses of the fabricated two-stage comparator are studied in detail to reveal limiting factors and corresponding mechanisms of n-/p-FETs on circuit performance. These results can provide valuable insights for the further development of GaN CL integrated circuits (ICs) for next-generation power conversion systems.

The gate terminal of mainstream Schottky-type p-GaN gate high-electron-mobility transistor (HEMT) is particularly vulnerable to the gate voltage ringing during the fast-switching transient due to its narrow gate voltage headroom for safe operation. In this work, a new gate driver circuit with expanded gate voltage headroom and suppressed gate-loop oscillation/ringing is proposed. The new design is based on a dynamic two-stage turn-on process enabled by a GaN lateral field-effect rectifier (L-FER)-resistor pair that can self-adaptively adjust the gate charging speed according to the real-time gate voltage, enabling fast charging during the initial turn-on stage and slow charging when the gate is near complete turn on. The latter stage effectively suppresses the gate-loop oscillation to enable an elevated gate turn-on voltage for a stronger yet safe gate overdrive to suppress the dynamic R_ON degradation in the GaN HEMT. Such a dynamic two-stage gate voltage profile can be realized without additional active sensing or control. The GaN L-FER is implemented with a low-voltage GaN HEMT in the diode mode that is free of reverse recovery issues. Equipped with this dynamic two-stage gate driver, the fast-switching potential of the GaN HEMT can be fully unlocked to reduce the switching loss without gate overstress; meanwhile, the switching oscillation can also be suppressed significantly.

Since thyristors have better performance than fully controllable devices in terms of on-state resistance and cost, designing thyristor-based solid-state circuit breakers (TSCBs) to protect dc microgrids has become gradually popular. In this article, a new bidirectional TSCB with four significant advantages is proposed. First, it could reliably and actively interrupt both the operating and fault currents with simple operation sequences; thus, ensuring high reliability and controllability. Second, the currents at input and output sides of the proposed TSCB are rapidly suppressed immediately after it starts working, so the source or load sides will not be threatened by large surge currents. Third, both the auxiliary thyristors and capacitors in the proposed TSCB will automatically restore to their initial states after the current breaking processes, which ensures the proposed TSCB has a reclosing protection function. Fourth, it has a low conduction loss, and is therefore effective. All these advantages make the proposed TSCB one great candidate to protect dc microgrids. The detailed topology introduction, circuit modeling analyses, experimental results, and comparative study are presented.

The forward gate human-body-model (HBM) electrostatic discharge (ESD) robustness and mechanisms of the Schottky-type p-GaN gate HEMTs are investigated. Unexpectedly, the transient forward gate leakage current ( I _G ) is high during appreciable, yet non-destructive, discharge events. To characterize the elevated I _G more comprehensively, we use SiC MOSFETs to devise a new pulsed I-V test system. This system is capable of generating voltage pulses with a rise time of ≤ 10 ns and width of < 100 ns, and a maximum pulse current of 26 A. The pulsed I _G - V _G (gate voltage) characteristics’ temperature and time dependencies suggest that the high transient I _G is primarily governed by electron thermionic emission across the AlGaN barrier. This emission is stimulated by the dynamic capacitive V _G division within the two back-to-back junctions of the p-GaN gate stack rather than by the resistive V _G division observed in the steady-state conditions.

A human-body-model (HBM) electrostatic discharge (ESD) simulator using a SiC MOSFET as the main switch is realized, verified and applied. Compared with the electromechanical relay used in the conventional simulator, the SiC MOSFET presents no restriction from the mechanical contact, smaller size and lower cost. The SiC MOSFET enables a 3.3-ns rise time of the ESD current and a 2-kV ESD voltage, leading to a high-speed and high-voltage HBM ESD simulator. The proposed ESD simulator is verified by the current waveform specified in the JEDEC standard and by comparing the measured results with those from a standard simulator. Using the new simulator, the ESD robustness of Schottky-type p-GaN gate HEMTs is evaluated. The dominant factors for ESD robustness are identified from the dynamic discharge processes.

The high reverse-recovery charge ( Q_rr ) of the Si superjunction (SJ) mosfet s’ body diode leads to exacerbated switching loss and even destructive dynamic avalanche. In this article, we propose a GaN/Si-SJ cascode structure that combines the high-voltage Si SJ- mosfet s with a low-voltage GaN HEMT. Benefiting from introducing GaN HEMT, the GaN/Si-SJ cascode structure features zero Q_rr at moderate current levels and substantially suppressed Q_rr at high current levels. Such a significant improvement in the reverse-recovery process leads to a more than 50% reduction in switching loss and significantly enhanced hard-commutation robustness simultaneously.

The GaN/SiC cascode device featuring a low-voltage (LV) enhancement-mode (E-mode) GaN high-electron-mobility transistors (HEMT) and a high-voltage (HV) SiC JFET has the unique capability of delivering thermally stable threshold voltage, avalanche capability, zero reverse recovery charge ( Q _rr ), and fast switching speed simultaneously. However, the lack of avalanche capability in the LV GaN HEMT presents a challenging issue, namely the negative gate overstress of the HV SiC JFET during the switching process, which raises reliability concerns. A clamping unit based on a Si Zener diode can provide gate protection for JFET but inevitably increases the switching loss significantly due to the reverse-recovery process of the Si Zener diode. This article presents a new gate protection design based on a Si bi-directional Zener diode that can clamp the gate voltage of JFET without introducing the reverse-recovery process. Therefore, the gate of JFET can be protected while the switching performance of the cascode device is not compromised, as verified by the experiment results.