Weng-Fai Wong
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Previous Organizations / Institutes
The organizations / institutes from the scholar's other articles in the past ten years
Weng-Fai Wong has a total of 150 co-authors. Here are the top co-authors by number of shared publications:
- Bingsheng He
National University of Singapore, Singapore, Singapore
11 shared publications - Yao Chen
School of Computing, National University of Singapore, Singapore
11 shared publications - Tao Luo
Institute of High Performance Computing, Agency for Science, Technology and Research
10 shared publications - Nhut-Minh Ho
School of Computing, National University of Singapore, Singapore
8 shared publications - Rick Siow Mong Goh
Agency for Science, Technology and Research (A*STAR)
7 shared publications - Zhanglu Yan
School of Computing, National University of Singapore, Singapore, Singapore
7 shared publications
Latest Publications
- Open Access
- 9 November 2026
- Published byย Association for Computing Machinery (ACM)
- p. 9471-9480
ShiftLIF: Efficient Multi-Level Spiking Neurons with Power-of-Two Quantization
- 9 November 2026
- Published byย Association for Computing Machinery (ACM)
- p. 9471-9480
Open AccessShiftLIF: Efficient Multi-Level Spiking Neurons with Power-of-Two Quantization
- 1 November 2026
- Published byย Institute of Electrical and Electronics Engineers (IEEE)ย inย IEEE Transactions on Parallel and Distributed Systems
- Vol.ย 37 ย (11) , 2390-2406
FairCache : Demystifying Cache-Induced Unfairness in Multi-Tenant Large Language Model Serving
- 1 November 2026
- Published byย Institute of Electrical and Electronics Engineers (IEEE)ย inย IEEE Transactions on Parallel and Distributed Systems
- Vol.ย 37 ย (11) , 2390-2406
FairCache : Demystifying Cache-Induced Unfairness in Multi-Tenant Large Language Model Serving
- Open Access
- 13 July 2026
- Published byย Association for Computing Machinery (ACM)
- p. 361-373
CARBS: Compiler Autotuning via Randomized Biased Search
- 13 July 2026
- Published byย Association for Computing Machinery (ACM)
- p. 361-373
Open AccessCARBS: Compiler Autotuning via Randomized Biased Search
- Open Access
- 12 April 2026
- Published byย Association for Computing Machinery (ACM)
- p. 5334-5345
Energy-Efficient and Dequantization-Free Quantization of LLMs: A Spiking Neural Network Approach to Salient Value Mitigation
- 12 April 2026
- Published byย Association for Computing Machinery (ACM)
- p. 5334-5345
Open AccessEnergy-Efficient and Dequantization-Free Quantization of LLMs: A Spiking Neural Network Approach to Salient Value Mitigation
- 18 March 2026
- Published byย Institute of Electrical and Electronics Engineers (IEEE)ย inย IEEE Transactions on Parallel and Distributed Systems
- Vol.ย 37 ย (5) , 1205-1218
Texplorer: Efficient Tensor Program Optimization for GPUs Using a Highly Constrained Search Space
Optimizing tensor programs for deep learning inference is costly, often requiring hours of search over massive search spaces ($>\! 10^{10}$ ). Prior machine learning–guided approaches are stochastic and inefficient because they treat both the search and programs as black boxes, overlooking two key properties: 1) the search space is highly structured, with large regions of invalid or low-performing configurations, and 2) tensor programs exhibit analyzable patterns in memory access and pipelined execution. We present Texplorer, a deterministic tensor program optimizer that exploits these structures for robust and efficient search. Texplorerintroduces a three-stage pruning algorithm to eliminate invalid, redundant, and inefficient candidates, shrinking the search space from billions to thousands. It replaces costly learned models with a lightweight analytical cost model that captures GPU pipeline and memory behavior, enabling accurate, training-free performance prediction and strong cross-operator generalization. Finally, Texplorerintegrates pruning and cost modeling into a one-pass analytical evaluation pipeline that ranks all remaining candidates, enabling rapid convergence without iterative retraining or stochastic sampling. Across 144 operators and 11 DNNs on NVIDIA V100, A100, and H100 GPUs, Texplorermatches state-of-the-art performance while reducing search time by up to$300\times$ . An enhanced variant, Texplorer$^{+}$ , further improves performance by up to 3.1% with up to$72\times$ faster tuning.- 18 March 2026
- Published byย Institute of Electrical and Electronics Engineers (IEEE)ย inย IEEE Transactions on Parallel and Distributed Systems
- Vol.ย 37 ย (5) , 1205-1218
Texplorer: Efficient Tensor Program Optimization for GPUs Using a Highly Constrained Search Space
Optimizing tensor programs for deep learning inference is costly, often requiring hours of search over massive search spaces ($>\! 10^{10}$ ). Prior machine learning–guided approaches are stochastic and inefficient because they treat both the search and programs as black boxes, overlooking two key properties: 1) the search space is highly structured, with large regions of invalid or low-performing configurations, and 2) tensor programs exhibit analyzable patterns in memory access and pipelined execution. We present Texplorer, a deterministic tensor program optimizer that exploits these structures for robust and efficient search. Texplorerintroduces a three-stage pruning algorithm to eliminate invalid, redundant, and inefficient candidates, shrinking the search space from billions to thousands. It replaces costly learned models with a lightweight analytical cost model that captures GPU pipeline and memory behavior, enabling accurate, training-free performance prediction and strong cross-operator generalization. Finally, Texplorerintegrates pruning and cost modeling into a one-pass analytical evaluation pipeline that ranks all remaining candidates, enabling rapid convergence without iterative retraining or stochastic sampling. Across 144 operators and 11 DNNs on NVIDIA V100, A100, and H100 GPUs, Texplorermatches state-of-the-art performance while reducing search time by up to$300\times$ . An enhanced variant, Texplorer$^{+}$ , further improves performance by up to 3.1% with up to$72\times$ faster tuning.- 24 February 2026
- Published byย Institute of Electrical and Electronics Engineers (IEEE)ย inย IEEE Transactions on Knowledge and Data Engineering
- Vol.ย 38 ย (5) , 2865-2879
Geometric Partition for Billion-Scale Approximate Nearest Neighbor Search
Large-scale approximate nearest neighbor search (ANNS) has become a fundamental operation in a wide range of modern applications, including recommendation systems and large language models. Partition-based indexes have emerged as a popular solution for billion-scale ANNS tasks, serving as the basis for many ANNS approaches. However, our analysis indicates that, to achieve optimal search performance on billion-scale datasets, an extremely large number of partitions (tens or even hundreds of millions) is often required for fine-grained partitioning of the feature space. Relying on full-precision distance calculations for constructing and querying such a large number of partitions imposes significant time costs. In this work, we propose a novel geometric distance inference mechanism that leverages geometric relationships to expedite distance computations between the vector and space partitions. By reusing intermediate or offline-computed distance information, this method substantially reduces the overhead of full-precision calculations. We also introduce a clustering paradigm for generating space partitions that incorporates this geometric distance pattern, which can be seamlessly integrated with other indexing schemes such as vector quantization and proximity graphs. Through detailed complexity analysis and extensive experiments on billion-scale datasets, we confirm the efficiency of our geometric index (GI) design. Empirical results show that GI-based solutions consistently surpass various baseline methods on search efficiency. In particular, they offer considerable acceleration (exceeding a factor of 2.0) at high recall levels (e.g., Recall10@10 = 95%) to partition-based solutions, while also demonstrating comparable or superior query throughput relative to leading graph-based indexes.
- 24 February 2026
- Published byย Institute of Electrical and Electronics Engineers (IEEE)ย inย IEEE Transactions on Knowledge and Data Engineering
- Vol.ย 38 ย (5) , 2865-2879
Geometric Partition for Billion-Scale Approximate Nearest Neighbor Search
Large-scale approximate nearest neighbor search (ANNS) has become a fundamental operation in a wide range of modern applications, including recommendation systems and large language models. Partition-based indexes have emerged as a popular solution for billion-scale ANNS tasks, serving as the basis for many ANNS approaches. However, our analysis indicates that, to achieve optimal search performance on billion-scale datasets, an extremely large number of partitions (tens or even hundreds of millions) is often required for fine-grained partitioning of the feature space. Relying on full-precision distance calculations for constructing and querying such a large number of partitions imposes significant time costs. In this work, we propose a novel geometric distance inference mechanism that leverages geometric relationships to expedite distance computations between the vector and space partitions. By reusing intermediate or offline-computed distance information, this method substantially reduces the overhead of full-precision calculations. We also introduce a clustering paradigm for generating space partitions that incorporates this geometric distance pattern, which can be seamlessly integrated with other indexing schemes such as vector quantization and proximity graphs. Through detailed complexity analysis and extensive experiments on billion-scale datasets, we confirm the efficiency of our geometric index (GI) design. Empirical results show that GI-based solutions consistently surpass various baseline methods on search efficiency. In particular, they offer considerable acceleration (exceeding a factor of 2.0) at high recall levels (e.g., Recall10@10 = 95%) to partition-based solutions, while also demonstrating comparable or superior query throughput relative to leading graph-based indexes.
- Open Access
Kirin: Improving ANN efficiency with SNN Hybridization
Artificial neural networks (ANNs), particularly large language models (LLMs), demonstrate powerful inference capabilities but consume substantial energy. Conversely, spiking neural networks (SNNs) exhibit exceptional energy efficiency due to their binary and event-driven characteristics, thus motivating the study of ANN-to-SNN conversion. In this process, quantization plays a pivotal role, mapping LLMs' floating-point parameters to discrete SNN parameters via the temporal dimension of the time window. However, several challenges remain in the conversion process: (i) converting high bit-width quantization values into binary spikes requires longer time windows, increasing system latency; and (ii) the inherent trade-off between the information loss of single-spike schemes and the energy costs of multi-spike ones in SNN. To address these challenges, we propose Kirin, a integer and spike hybrid based SNN to achieve accuracy lossless ANN-to-SNN conversion with time and energy efficiency. Specifically, we first propose a Spike Matrix Hybridization strategy that encoding low bit-width parameters that leading to small time window size into binary spikes while preserving the rest in integer format, thereby reducing the overall latency of SNN execution. Second, we introduce a silence threshold mechanism to regulate the timing of single-spike firing, ensuring the output is mathematically equivalent to the LLM's output and preserves accuracy. Experimental results demonstrate that Kirin, under a W4A4\&8 quantization setting, achieves near-FP16 accuracy while reducing energy consumption by up to 84.66\% and shortening time steps by 93.75\%.
Open AccessKirin: Improving ANN efficiency with SNN Hybridization
Artificial neural networks (ANNs), particularly large language models (LLMs), demonstrate powerful inference capabilities but consume substantial energy. Conversely, spiking neural networks (SNNs) exhibit exceptional energy efficiency due to their binary and event-driven characteristics, thus motivating the study of ANN-to-SNN conversion. In this process, quantization plays a pivotal role, mapping LLMs' floating-point parameters to discrete SNN parameters via the temporal dimension of the time window. However, several challenges remain in the conversion process: (i) converting high bit-width quantization values into binary spikes requires longer time windows, increasing system latency; and (ii) the inherent trade-off between the information loss of single-spike schemes and the energy costs of multi-spike ones in SNN. To address these challenges, we propose Kirin, a integer and spike hybrid based SNN to achieve accuracy lossless ANN-to-SNN conversion with time and energy efficiency. Specifically, we first propose a Spike Matrix Hybridization strategy that encoding low bit-width parameters that leading to small time window size into binary spikes while preserving the rest in integer format, thereby reducing the overall latency of SNN execution. Second, we introduce a silence threshold mechanism to regulate the timing of single-spike firing, ensuring the output is mathematically equivalent to the LLM's output and preserves accuracy. Experimental results demonstrate that Kirin, under a W4A4\&8 quantization setting, achieves near-FP16 accuracy while reducing energy consumption by up to 84.66\% and shortening time steps by 93.75\%.
- Open Access
RidgeWalker: Perfectly Pipelined Graph Random Walks on FPGAs
Graph Random Walks (GRWs) offer efficient approximations of key graph properties and have been widely adopted in many applications. However, GRW workloads are notoriously difficult to accelerate due to their strong data dependencies, irregular memory access patterns, and imbalanced execution behavior. While recent work explores FPGA-based accelerators for GRWs, existing solutions fall far short of hardware potential due to inefficient pipelining and static scheduling. This paper presents RidgeWalker, a high-performance GRW accelerator designed for datacenter FPGAs. The key insight behind RidgeWalker is that the Markov property of GRWs allows decomposition into stateless, fine-grained tasks that can be executed out-of-order without compromising correctness. Building on this, RidgeWalker introduces an asynchronous pipeline architecture with a feedback-driven scheduler grounded in queuing theory, enabling perfect pipelining and adaptive load balancing. We prototype RidgeWalker on datacenter FPGAs and evaluated it across a range of GRW algorithms and real-world graph datasets. Experimental results demonstrate that RidgeWalker achieves an average speedup of 7.0x over state-of-the-art FPGA solutions and 8.1x over GPU solutions, with peak speedups of up to 71.0x and 22.9x, respectively. The source code is publicly available at https://github.com/Xtra-Computing/RidgeWalker.
Open AccessRidgeWalker: Perfectly Pipelined Graph Random Walks on FPGAs
Graph Random Walks (GRWs) offer efficient approximations of key graph properties and have been widely adopted in many applications. However, GRW workloads are notoriously difficult to accelerate due to their strong data dependencies, irregular memory access patterns, and imbalanced execution behavior. While recent work explores FPGA-based accelerators for GRWs, existing solutions fall far short of hardware potential due to inefficient pipelining and static scheduling. This paper presents RidgeWalker, a high-performance GRW accelerator designed for datacenter FPGAs. The key insight behind RidgeWalker is that the Markov property of GRWs allows decomposition into stateless, fine-grained tasks that can be executed out-of-order without compromising correctness. Building on this, RidgeWalker introduces an asynchronous pipeline architecture with a feedback-driven scheduler grounded in queuing theory, enabling perfect pipelining and adaptive load balancing. We prototype RidgeWalker on datacenter FPGAs and evaluated it across a range of GRW algorithms and real-world graph datasets. Experimental results demonstrate that RidgeWalker achieves an average speedup of 7.0x over state-of-the-art FPGA solutions and 8.1x over GPU solutions, with peak speedups of up to 71.0x and 22.9x, respectively. The source code is publicly available at https://github.com/Xtra-Computing/RidgeWalker.