Yida Li
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Yida Li has a total of 12 co-authors. Here are the top co-authors by number of shared publications:
- Aaron Voon-Yew Thean
Department of Electrical and Computer Engineering, National University of Singapore, 4 Engineering Drive 3, Singapore 117583, Singapore
2 shared publications - Baoshan Tang
Department of Electrical and Computer Engineering National University of Singapore Singapore 117576 Singapore
1 shared publication - Bo Xiong
Department of Electrical and Computer Engineering, National University of Singapore (NUS), Singapore 117583
1 shared publication - Chun-Huat Heng
Department of Electrical and Computer Engineering, National University of Singapore, Queenstown, Singapore
1 shared publication - Evgeny Zamburg
Department of Electrical and Computer Engineering, National University of Singapore, Singapore, Singapore
1 shared publication Hasita Veluri
Department of Electrical and Computer Engineering, National University of Singapore, 4 Engineering drive 3, Singapore, 117583, Singapore
1 shared publication
Latest Publications
- 8 January 2020
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. PP (00189200) , 1-11
A 7 x 7 x 2 mm³ 8.6-μW 500-kb/s Transmitter With Robust Injection-Locking-Based Frequency-to-Amplitude Conversion Receiver Targeting for Implantable Applications
A transmitter (TX)/receiver (RX) pair using galvanic coupling to achieve in-body to on-body body channel communication (I2O-BCC) for ultra-low power (ULP) miniaturized implanted applications is presented. The I2O-BCC enables low loss communication (<40 dB) within 10-40 MHz band and up to 10-cm in vivo communication distance using the body as a transmission medium. Injection locking (IL)-based frequency-to-amplitude (F2A) conversion demodulator is proposed in RX. It can handle more than 20% frequency variations exhibited by the TX frequency-shift keying (FSK) signals due to the lack of accurate off-chip reference. The packaged implanted TX measures 7 x 7 x 2 mm³. It contains a micro-battery, two micro-probes, and the designed SoC in 130-nm CMOS process. The in-body TX radio block consumes only 8.6 μW at 500 kb/s with an on-chip power management unit that exhibits a 45% power efficiency, while the on-body RX consumes 591.5 μW. The TX radio block power is 8x lower than previous works and achieves energy efficiency at 17.2 pJ/b with minimal bill of material (BOM).
- 8 January 2020
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. PP (00189200) , 1-11
A 7 x 7 x 2 mm³ 8.6-μW 500-kb/s Transmitter With Robust Injection-Locking-Based Frequency-to-Amplitude Conversion Receiver Targeting for Implantable Applications
A transmitter (TX)/receiver (RX) pair using galvanic coupling to achieve in-body to on-body body channel communication (I2O-BCC) for ultra-low power (ULP) miniaturized implanted applications is presented. The I2O-BCC enables low loss communication (<40 dB) within 10-40 MHz band and up to 10-cm in vivo communication distance using the body as a transmission medium. Injection locking (IL)-based frequency-to-amplitude (F2A) conversion demodulator is proposed in RX. It can handle more than 20% frequency variations exhibited by the TX frequency-shift keying (FSK) signals due to the lack of accurate off-chip reference. The packaged implanted TX measures 7 x 7 x 2 mm³. It contains a micro-battery, two micro-probes, and the designed SoC in 130-nm CMOS process. The in-body TX radio block consumes only 8.6 μW at 500 kb/s with an on-chip power management unit that exhibits a 45% power efficiency, while the on-body RX consumes 591.5 μW. The TX radio block power is 8x lower than previous works and achieves energy efficiency at 17.2 pJ/b with minimal bill of material (BOM).
- Open Access
- 15 November 2019
- Published by Springer Nature in Nature Communications
- Vol. 10 (1) , 5201
All WSe2 1T1R resistive RAM cell for future monolithic 3D embedded memory integration
3D monolithic integration of logic and memory has been the most sought after solution to surpass the Von Neumann bottleneck, for which a low-temperature processed material system becomes inevitable. Two-dimensional materials, with their excellent electrical properties and low thermal budget are potential candidates. Here, we demonstrate a low-temperature hybrid co-integration of one-transistor-one-resistor memory cell, comprising a surface functionalized 2D WSe2p-FET, with a solution-processed WSe2 Resistive Random Access Memory. The employed plasma oxidation technique results in a low Schottky barrier height of 25 meV with a mobility of 230 cm2 V−1 s−1, leading to a 100x performance enhanced WSe2p-FET, while the defective WSe2 Resistive Random Access Memory exhibits a switching energy of 2.6 pJ per bit. Furthermore, guided by our device-circuit modelling, we propose vertically stacked channel FETs for high-density sub-0.01 μm2 memory cells, offering a new beyond-Si solution to enable 3-D embedded memories for future computing systems.
- 15 November 2019
- Published by Springer Nature in Nature Communications
- Vol. 10 (1) , 5201
Open AccessAll WSe2 1T1R resistive RAM cell for future monolithic 3D embedded memory integration
3D monolithic integration of logic and memory has been the most sought after solution to surpass the Von Neumann bottleneck, for which a low-temperature processed material system becomes inevitable. Two-dimensional materials, with their excellent electrical properties and low thermal budget are potential candidates. Here, we demonstrate a low-temperature hybrid co-integration of one-transistor-one-resistor memory cell, comprising a surface functionalized 2D WSe2p-FET, with a solution-processed WSe2 Resistive Random Access Memory. The employed plasma oxidation technique results in a low Schottky barrier height of 25 meV with a mobility of 230 cm2 V−1 s−1, leading to a 100x performance enhanced WSe2p-FET, while the defective WSe2 Resistive Random Access Memory exhibits a switching energy of 2.6 pJ per bit. Furthermore, guided by our device-circuit modelling, we propose vertically stacked channel FETs for high-density sub-0.01 μm2 memory cells, offering a new beyond-Si solution to enable 3-D embedded memories for future computing systems.