Jeong-Min Jo

Maglev trains require precise position data to control their propulsion systems. Specifically, sensing accurate phase based on position is necessary, for which cross‐inductive loop coils are used. To minimize phase errors, the envelope of the received voltage must be a sinusoidal wave depending on the position. This letter proposes the shapes of transmitting and receiving coils and presents, through simulation and experimentation, that the shapes of the transmitting and receiving coils and the induced voltage are in a convolution.

The transportation system using the Long-stator linear motor propulsion system has the advantage of directly transmitting propulsion force to the vehicle regardless of adhesive friction at high speed, and is used for high speed maglev. However, the initial installation cost is high and as the length of the segmented stator increases, the operating efficiency and power factor are low, resulting in an increase in the capacity of the propulsion inverter and in operating costs. The paper proposes a section switching method using BCT (Bi-directional Controlled Thyristors) in order to minimize the length of the segmented stator. And in order to verify the excellence of section switching method using BCT, a small scale circular test-bed based on a linear motor was manufactured. The experimental result showed that the output current of the inverter fluctuates by motor impedance change when the vehicle moves between stator blocks, and a current ripple occurs due to a position error of the discontinuous position detection signal. In order to solve these problems, a position estimator using full-state observer was presented and the excellence was verified through a test using the test-bed.

In this paper, a simulation methodology and an electromagnetic compatibility qualification environment (EQE) are developed to verify the electromagnetic susceptibility of semicustom digital integrated circuits (IC) during the design phase. The immunity levels of the digital circuits are estimated by the functional failure and delay change caused by the external noise which is injected by bulk current injection (BCI) and direct power injection (DPI) methods. The model for the device under test (DUT), the standard cell parasitic model, and the equivalent circuit model of BCI and DPI test setup are developed for the IC immunity test. All test components and on-chip circuit models are linked by EQE to analyze the target DUT. The EQE can be applied to predict the immunity level of the design at the schematic level and postlayout level design. To validate the accuracy of the proposed simulation tool, EQE is applied to the design process of a clock divider (CKD) and a serial peripheral interface (SPI) circuits to verify their immunity levels. The CKD and SPI circuits are designed and fabricated using Magna 180 nm Complementary metal-oxide semiconductor (CMOS) technology. The immunity levels generated by the EQE are compared with the experimental measurement results. The comparison shows good agreement between simulation and measurement.

This paper shows a novel simulation method for bulk current injection (BCI) tests of I/O buffer circuits of mobile system memory. The simulation model consists of BCI probe, directional coupler, PCB, PKG, and IC. The proposed method is based on a behavioural I/O buffer model using a pulse generator as an input. A detailed simulation flow is introduced and validated through simulations performed on several injection probe loading conditions using a power decoupling capacitor and an on-chip decoupling capacitor.