Jens Wagner

This paper presents the analysis and design of an ultra-low-power injection-locked transmitter supporting ON-OFF keying (OOK) and frequency-shift keying (FSK) modulation for short-range sensor node applications. To achieve sub- $\mu $ W operation, this design incorporates an enhanced start-up crystal oscillator, allowing for aggressive duty cycling of the entire transmitter. The duty-cycling signal is generated by a nanowatt on-chip clock oscillator, effectively minimizing sleep-mode power consumption. Frequency tuning of injection-locked oscillators enables operation across multiple standard sub-GHz bands, including the MedRadio band at 400 MHz and the ISM bands at 433 MHz and 915 MHz—within a single architecture, which, to the best of the authors’ knowledge, has not been previously reported. With an optimized injection phase sequence, the carrier generation block, operating with a stabilized reference signal, achieves a sub-11 ns settling time. To prove the concept, the transmitter is fabricated in 130 nm technology, occupying a core area of 0.133 mm². Operating from a 0.25--0.9 V supply, the transmitter delivers an output power of −23.3 dBm at 432 MHz. At 1 Mb/s, it consumes 183 $\mu $ W in continuous operation and only 435 nW in duty-cycled mode with a duty cycle of 0.09%. With optimized start-up and switching, the transmitter achieves a data rate of 85 Mb/s and an energy efficiency of 2.57 pJ/bit— representing, to the best of the authors’ knowledge, the highest energy efficiency and data rate among sub-GHz ultra-low-power transmitters reported to date.

This paper presents the analysis, design, and characterization of an on-chip ultra-low-power clock oscillator for sensor nodes, implemented in 130 nm BiCMOS technology. The design employs a multi-stacked inverter-based ring oscillator topology which utilizes variable RC features to tune the oscillation frequency. It is demonstrated that incorporating resistive coupling in the inverter stages helps to minimize frequency deviation around 12.1-13.5% for 10% of power supply variations and consequently achieves frequency stability improvement. To the best knowledge of the authors, this is the first time that a multi-stacked technique is utilized in the inverter stages of an oscillator to make the leakage current negligible reducing power consumption. With an adaptive delay line, the design is enabled to produce an adjustable duty-cycling output. The proposed oscillator consumes 510pW from a 0.35V power supply at 810 Hz operation frequency and achieves a power efficiency of 0.63 nW/kHz, positioning it among the most efficient Hz-to-kHz oscillators. The design occupies an area of 0.038 mm².

The noise theory and measurement results of an ultralow-power receiver analog frontend core based on an switched injection-triggered oscillator (SITO) integrated in GlobalFoundries 22 nm fully depleted silicon on insulator (FD-SOI) technology are presented. Both an analytical time-domain description and a frequency-domain noise analysis for the SITO are derived. Using these, the influence of noise on the ramp-up behavior of the SITO is analyzed using a Monte Carlo simulation to predict the input sensitivity. The simulation runtime was reduced by a factor of 2400 compared with circuit simulations. An analog SITO receiver frontend with a Hartley oscillator powered from 0.5 V is designed and implemented. It achieves an input sensitivity of $-$ 93 dBm (measured, without coding) and a dc energy consumption per bit of 65 pJ/bit (measured), which improves the energy efficiency of state-of-the-art analog receiver frontends by a factor of 4.3. The measured 3 dB input filtering bandwidth is 136 kHz. The consumed dc power scales with data rate due to bitwise duty cycling from 2 nW at 10 bps up to 3.9 $\upmu$ W at 32 kbps (all measured), making it a perfect candidate for wakeup receivers. The noise model is validated by comparing the ramp-up time from measurements with the Monte Carlo simulation.

This research presents and examines the first power and speed adaptive 60 GHz receiver, combining the potential of high data rates with low energy consumption. Hence, enabling a range of Tactile Internet applications such as a compact wireless robotic skin. Designed and fabricated in a 22 nm fully depleted silicon-on-insulator (FD-SOI) CMOS process, the required area is only 0.67mm ² . Low energy consumption is achieved by using on-off keying (OOK) and aggressive duty cycling. For data rates up to 25 Mbps, synchronization is achieved by oversampling. In this case, the sampling clock is directly related to the data rate. The duty cycle is generated from the sampling clock and defines the average energy consumption. Consequently, a truly data rate dependent energy consumption can be achieved, which is especially beneficial in low communication load scenarios. At a maximum data rate of 2.8 Gbps, the energy consumption is 15.3 mW, while at 25 kbps the receiver consumes only 1.1 μW. Moreover, the achieved sensitivity is -20.5 dBm at 2.8 Gbps for a bit error rate (BER) below 1E-12 and -25 dBm at 25 kbps respectively.

This article presents and investigates a $V$ -band transmitter (TX) for low-power wireless communication supporting on–off keying (OOK) and four-/eight-level pulse amplitude modulation (PAM4/8). To prove the concept, the circuit is implemented in a 22-nm fully depleted silicon-on-insulator (FD-SOI) complementary metal oxide semiconductor (CMOS) technology. The TX consumes 11.7 mW at full speed. Furthermore, the TX supports low-power mode with as low as 700 nW of dc power. The maximum data rate is 2 Gb/s. By applying dynamic data rate to dc-power adaptivity (DDDA), the dc power can be significantly reduced as the data rates decreases. This maintains the energy-per-bit below 10 pJ/b for data rates greater than 100 kb/s with a best value of 3.9 pJ/b and allows the dc power to be greatly reduced down to 700 nW at data rates below 20 kb/s. The measured maximum transmission power is 6.5 dBm. Moreover, the TX achieves 10-dBm effective isotropic radiated power (EIRP) with an on-chip 3-D antenna. The core area of the TX is only 0.19 mm $^2 $ . To the best knowledge of the authors, the proposed TX is the first reported TX with DDDA and achieves the lowest dc power in comparison to similar designs that have been reported to date.

This paper investigates a 60 GHz low-power broadband low noise amplifier (LNA) with variable gain control. To prove the concept, the circuit is implemented in a 22 nm fully depleted silicon on insulator (FD-SOI) CMOS technology. It supports broadband operation at 60 GHz achieved by gain peaking (gain distribution) technique. By tuning some key matching networks of the amplifier, the peak gain of each stage was distributed to different frequencies resulting in an overall broadband frequency response. The circuit consists of three cascaded cascode amplifier stages. Matching networks were optimized regarding bandwidth and noise figure. The transistor back-gate was used for LNA designs to switch the circuit to low-power standby mode. This avoids the problems of front-gate based switching regarding voltage breakdown and circuit stability. Additionally, simultaneous realization of variable gain control at such high frequencies was achieved via the back-gate. Compared to the front-gate based, the back-gate based variable gain control can deliver a continuous fine-tuning of the gain while requiring less accuracy or resolution of the control voltage. In the measurement, The gain was successfully tuned from 20 dB down to −25 dB via the back-gate. At a DC power of 8.1mW from a nominal supply of 1V, the LNA provides a peak gain of 20 dB, a bandwidth of 18.5 GHz, and a minimum noise figure of 3.3 dB. When biased at a reduced DC supply of 0.4V, the presented circuit consumes only 2.5mW of DC power, and still provides a power gain of 10 dB and a minimum noise figure of around 4.5 dB. By switching to standby mode, the LNA consumes 850 µW of DC power at the nominal supply and 240 µW at the reduced supply. The LNA compares well against previously reported designs by showing the lowest noise figure with competitive gain, bandwidth and DC power. To the authors’ knowledge, this is the first 60 GHz LNA featuring joined variable gain control and switching capability via solely back-gate biasing.

This research analyzes the mutual self-organized synchronization of phase-locked loops (PLLs) in the presence of variations in the free-running frequency of a PLL. In contrast to traditional synchronization methods that rely on a reference signal, this study investigates the synchronization dynamics that arise solely from the interactions of PLL nodes within a network. Previous research has proposed theoretical frameworks that can predict the synchronized states of such designs. However, these frameworks do not account for the dynamic behavior that occurs during initial synchronization. To address this gap, this work proposes a constraint that refines the understanding of initial synchronization. The results of this analysis show that there is a maximum detuning between free-running frequencies up to which synchronization is possible. Furthermore, this analysis indicates that detuning not only affects the range of time delays at which stable synchronized states emerge between PLL nodes, but also limits the allowable range of initial phase differences for stable synchronization. In the cases studied, a frequency difference of 1.56% reduces the probability of achieving stable synchronized states through self-organized synchronization to 73.5%, while no stable synchronization can be achieved at a frequency difference greater than 2.65%. The study underscores the critical importance of operating ranges when implementing mutual coupling. In particular, all PLL nodes must have overlapping lock ranges to achieve stable synchronization. It also emphasizes the need for accurate analysis of hold and lock ranges in relation to the time delays between coupled PLL nodes.

This article discusses the phase noise (PN) characteristics of mutually delay-coupled phase-locked loop (PLL) nodes operating at 24 GHz. It examines the effect of mutual synchronization on PN. A behavioral model is derived that describes the critical dynamics of synchronized nodes. Power spectral density (PSD) measurements of mutually synchronized PLL nodes show that mutual coupling improves the PN, while unidirectional coupling increases the PN by about 3 dB per additional node. The long-term stability of the frequencies of individual nodes within the network is also studied, and no significant frequency differences are observed in stable synchronized states. This research shows that the time delay between nodes has no significant effect on the PN, but only on the synchronized state and its characteristics. The network topology also affects the dynamics, with different improvements in PN depending on the topology. The maximum improvement observed is 14.48 dB. Overall, the results suggest that mutually delay-coupled PLL nodes have the potential to provide stable, accurate, and robust synchronization in a range of applications, such as spatially distributed Internet of Things (IoT) devices and sensors. For research on advanced technologies that require precise and synchronized communications, these results have significant implications.

Synchronization is one of the most challenging aspects of distributed systems in terms of their scalability. Minimal uncertainties can lead to problems or failures regarding data consistency in globally operating data centers or in distributed sensor arrays. Existing approaches to address these challenges are based on hierarchical synchronization concepts which are well understood and have reached technical maturity, but have the disadvantage of having a single point of failure. However, especially for critical infrastructure or backup more resilient solutions are required. Mutual synchronization where oscillators in a network are coupled bidirectionally without a reference have been considered. Due to the flat hierarchy such systems do not have a single point of failure. This work studies how hierarchical synchronization can be combined with architectures implementing mutual synchronization. A network of three mutually coupled 24 GHz oscillators is used to study how injecting a reference signal into one oscillator affects the dynamics. This can be quantified by analyzing in which range of frequencies the network of mutually coupled oscillators can follow the reference frequency. Measurements on a ring and chain network topology forced by an external reference oscillator shown here are in good agreement with the predictions of a nonlinear dynamical model.

This letter presents a feasibility study for a 62 GHz power amplifier (PA) in a 22 nm CMOS technology with integrated data modulation via the back-gate. The proposed PA consists of two pseudo-differential cascode stages, and provides a peak gain of 23.3 dB, a Psat of 13.6 dBm and a peak PAE of 28.3%. The PA consumes 96 mW from a 2 V VDD at its saturation. Thanks to the transistor back-gate, the PA can be dynamically switched on and off by increasing the threshold voltage through the back-gate. This avoids AC ground, gain and stability problems caused by conventional front-gate switching. In off-mode it draws 2.5% of its peak DC power. Rise-and fall-times of 1 ns were measured. The possibility of back-gate based modulation was experimentally demonstrated, showing that the PA can be used as a single device transmitter. Compared to previously reported works the PA shows one of the highest PAE and excellent linearity. To the best knowledge of the authors, this is the first investigation of a 60 GHz PA with data modulation via the back-gate.