Yongwoo Lee

Ion‐gated transistors inherently exhibit time‐dependent behavior governed by ionic motion associated with electric double‐layer formation; however, their practical implementation has been limited by insufficient control over ionic dynamics and poor compatibility with scalable thin‐film integration. Here, we present carbon nanotube (CNT) solid‐ion‐gated transistors (sIGTs) that allow the wide‐range engineering of ionic dynamics while remaining fully compatible with wafer‐scale thin‐film processing. Tunable ionic conductance is achieved by ionic content engineering in the film and thickness scaling into the sub‐micron regime, enabling ionic time constants from microseconds to milliseconds. CNT sIGTs demonstrate robust DC operation at low ionic content with an optimized polymer matrix and wafer‐scale fabrication on flexible substrates. Frequency‐dependent gate modulation governed by ionic conductance is systematically investigated through electrical impedance spectroscopy and small‐signal analysis, including a comparison of the −3 dB cutoff frequency and the transit frequency. This analysis provides direct insight into the relationship between ionic conductance and frequency‐dependent device response, exhibiting consistent trends across both two‐terminal and three‐terminal device configurations. Monolithic three‐dimensional integration of two‐tier CNT sIGTs with engineered dynamic responses is demonstrated as a compact dual‐timescale physical reservoir for neuromorphic computing that enables classification of time‐varying inputs using a single readout layer.

Monolithic three‐dimensional integration demands embedded memory technologies that achieve extreme density scaling under limited back‐end‐of‐line thermal budget. Atomic layer deposition‐grown amorphous oxide semiconductors (AOS) are attractive for this purpose because of their excellent conformality and intrinsically low off‐state current I _OFF, enabling vertical channel transistors (VCTs) for capacitor‐less gain‐cell memory operation. However, in VCT, oxygen‐deficient AOS channels required for low leakage and high conductivity coexist with oxygen‐rich dielectric sidewalls, introducing a fundamental materials‐stack challenge associated with oxygen‐vacancy‐induced instability and parasitic oxidation at electrode interfaces. Indium tin oxide (ITO) offers a balance between low leakage and high carrier mobility, yet is particularly vulnerable to oxygen‐migration‐induced degradation in vertical geometries. Here, we introduce an oxygen‐tunnel stack based on SiN/SiO ₂ /SiN layers that spatially regulates oxygen transport. This architecture stabilizes oxygen vacancies in the ITO channel while suppressing electrode oxidation, enabling a record‐high current density of 436 µA/µm and a negligible threshold voltage shift of less than 50 mV after 10 ⁷ bias‐stress cycles. A gain‐cell memory demonstrated retention exceeding 648 s and endurance beyond 1200 cycles enabled by the exceptionally low I _OFF of 2.6 × 10 ⁻¹⁹ A/µm. A Si‐ITO hybrid gain‐cell integration framework was developed and evaluated, demonstrating the feasibility and system‐level benefits of incorporating oxygen‐regulated ITO VCTs into Si‐based embedded memory and compute‐in‐memory architectures.

Two-dimensional (2D) indium selenide (In₂Se₃) has great potential for next-generation processing-in-memory applications owing to high intrinsic carrier mobility and strong ferroelectricity. However, the lack of wafer-scale, back-end-of-line (BEOL) compatible growth and inherent polarization-induced hysteresis limit their viability in logic circuits. Here, we report thermal evaporation of a non-ferroelectric κ-phase In₂Se₃ film that forms uniformly over 4-inch wafer-scale at κ-phase formation with an indirect bandgap of 1.45 eV and n-type conduction. The unique atomic arrangement suppresses spontaneous polarization, eliminating hysteresis in field-effect transistors (FETs). The κ-In₂Se₃ FETs exhibit enhancement-mode operation, high field-effect mobility of 39.3 cm² V⁻¹ s⁻¹, and stable switching over 1000 cycles, enabled by reduced trap states and contact resistance. By integrating κ-In₂Se₃ with a p-type selenium-alloyed tellurium oxide FET, we demonstrate a complementary inverter with full-swing operation and high voltage gain. These results establish κ-In₂Se₃ as a scalable 2D semiconductor platform for BEOL-compatible logic integration.

Atomically thin 2D semiconductors enable excellent electrostatic control even in highly scaled transistors with few‐nanometer gate lengths. The electrical characteristics of 2D transistors can vary significantly with the number of layers, yet how device behavior evolves with channel thickness remains statistically unexplored. This limitation mainly arises from the difficulty of obtaining large numbers of single‐crystal flakes with well‐controlled thickness and fabricating devices. Here, we demonstrate the thickness‐dependent electrical characteristics of single‐flake MoS ₂ transistors correlating optical observables with the monolayer (ML) numbers. The optical intensity serves as an indicator of flake thickness for identifying the number of MLs, while algorithm‐based filtering of blurry edges and non‐uniform intensities enables the selection of high‐quality flakes. The filtered flakes are subsequently grouped into distinct thickness clusters based on their optical intensity distributions. The resulting thickness clusters are validated by atomic force microscopy, yielding flakes spanning 3–8 MLs. Automated device layout generation allows the electrical characterization of 1615 transistors selected from over 120000 flakes, providing insight into thickness‐dependent charge carrier injection and transport behavior. Our findings offer a statistically grounded framework linking flake thickness to electrical characteristics and demonstrate the utility of readily accessible optical microscopy for accelerating 2D semiconductor device research.

2T0C gain cell memory based on amorphous oxide semiconductor vertical channel transistors (VCTs) has emerged as a promising high-density embedded dynamic access memory solution for memory-centric computing systems, monolithically integrated atop silicon logic. This capacitor-less memory offers long retention time and a compact 4F² cell footprint, enabling low-power and area-efficient integration above logic circuits. In this work, amorphous indium tin oxide VCTs and 2T0C gain cells with hole diameters scaled down to 150 nm were fabricated. However, scaling the hole diameter caused residual etch by-products to accumulate along the channel sidewalls, degrading the subthreshold swing and on-state current. To mitigate this issue, a sidewall cleaning process was introduced to effectively remove the residues. The treatment improved the VCT on-state current by over three orders of magnitude and enabled stable single- and two-bit memory operation with retention time exceeding 160 s.

The performance of organic electrochemical transistors (OECTs) is fundamentally constrained by a trade-off between transconductance and temporal response. While increasing channel thickness enhances its capacitance and thereby amplifies transconductance, it simultaneously impedes ion transport kinetics, leading to slower switching speeds. Here, we present a three-dimensional electrolyte-surrounded OECT architecture that redefines ion transport dynamics by enabling multidirectional ion doping to the channel for efficient and rapid switching. Our proposed approach achieves a remarkable enhancement in the operational bandwidth of OECTs, reaching 26 kHz while preserving their high transconductance, notably using a commercially available conductive polymer, poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate). This is enabled by micro/nanostructured channel design that enhances ion accessibility and minimizes parasitic effects. This advancement allows for continuous, wide-frequency neural signal recording from peripheral nerves. This work offers a robust strategy for achieving both high transconductance and fast switching in OECTs, establishing a foundation for the development of next-generation, high-speed bioelectronic interfaces.

Atomically thin two-dimensional semiconductor molybdenum disulfide (MoS₂) is considered an ideal n-type channel material for field-effect transistors (FETs) due to its immunity to short-channel effects by dangling bond-free surface. However, sulfur atom dissociation or nonideal film deposition can easily lead to sulfur vacancies (SVs) in the MoS₂ film. These crystal imperfections create defects in the electronic structure, thereby limiting the utility of this promising material. We introduce an electron-withdrawing benzenethiol (BT) to repair the vacancies with the exact missing atoms at 200°C─marking the lowest process temperature for complete SV repair. These thiol groups actively and selectively bond with the vacant sites due to their self-assembly nature. Notably, we found that the fluorination of BT weakens the S-C bond as the BT withdraws electrons from the sulfur side. This enables a low-temperature annealing process to detach the headgroups from the MoS₂ surface. The atomic ratio of MoS₂ was recovered from 1.68 to 1.98, leading to an ideal subthreshold swing of MoS₂ FETs 62.5 mV·dec^-1. The proposed SV repair process, repeatedly applicable between fabrication steps for its low process temperature, unveils the potential of the BEOL MoS₂ FETs with a nearly ideal atomic ratio adhering to their thermal budget.

This letter presents the fabrication process of carbon nanotube-based thin-film transistors (CNT-TFTs) with direct-printed CNT channels on flexible substrates and investigates the implications of dual-gating effects. Enhancing the electrical percolation of the nanotube network channel is achieved through a post-annealing process, which includes thermal treatment and solvent immersion. Introducing a thin polymer passivation layer enhances the device’s electrostatic characteristics, eliminating hysteresis. Compared to single-gate CNT-TFTs, the dual-gate configuration allows for full depletion operation. This results in a reduced subthreshold slope and an increased on/off current ratio. These findings offer valuable insights into leveraging dual-gating effects for developing printed CNT-TFT circuits, with potential applications in high-performance, low-power, large-area, and flexible electronic systems.