Holger Rücker

This letter presents a 206.5–220.5-GHz fundamental differential Colpitts oscillator in a cascode topology implemented in a 130-nm SiGe HBT technology with f_t/fmax of 350/450 GHz. Base inductors at the common-base (CB) stages are used to provide an inductive load at the output of the common-emitter (CE) stage, hence, boosting the output power by 27%. The resonant tank is embedded straight on top of the devices, reducing layout parasitics and resulting in a compact and efficient oscillator core layout. The oscillator provides a peak output power of 7 dBm at 208 GHz, 7.4% peak dc-to-RF efficiency at 220 GHz, and 6.55% tuning range (TR). At peak efficiency, the oscillator delivers an output power of 5.7 dBm with 50-mW dc power consumption and a phase noise (PN) of -90.2/-110 dBc/Hz at 1-/10-MHz offset, respectively. To the best of the authors’ knowledge, the presented oscillator has the best PN figure-of-merit (FoM) of -182.1 dBc/Hz at 1-MHz offset in a SiGe/CMOS technology above 200 GHz. It occupies a total area of 0.086 mm², including the RF pad, and an ultracompact core size of 0.0049 mm².

This work focuses on a systematic analysis of the potential as well as the limitations of modern SiGe HBT devices for broadband passive room-temperature detection in the lower THz range. Multiple necessary conditions need to be fulfilled to facilitate broadband passive imaging with a sufficiently low in-band NEP, which refer to various technology-driven device operation aspects, including the rectification process at THz frequencies and low-frequency analysis. Considering a strong frequency dependence of the devices' inherent rectification potential, an in-depth understanding and proper modeling of the device internal parasitics in combination with antenna-detector co-design aspects are crucial for successful detector implementation. For that purpose, a simplified nonlinear high-frequency detector model was applied for the device operating not only in the classical forward-active region but also in deep saturation (cold operation). The complete detector was implemented in a modern high-speed 130 nm SiGe HBT technology with $f_{t}/f_{max}$ of 470/650 GHz. It comprises two independent orthogonal polarization paths within a single dual-polarization lens-coupled on-chip antenna to operate with unpolarized passive illumination. With the aid of an efficient antenna-circuit co-design, a close-to-optimum detector performance in a near-THz fractional bandwidth can be achieved, as experimentally verified in free-space with frequency-tunable coherent CW sources. In particular, the detector optical NEP for each independent polarization path was measured across 200–1000 GHz reporting state-of-the-art values of 2.3–23 pW/ $\mathrm{\sqrt{Hz}}$ and 4.3–45 pW/ $\mathrm{\sqrt{Hz}}$ with the device operating in the forward-active range and in saturation, respectively. This, in combination with the de-embedded equivalent noise bandwidth of 512 GHz centered around 430 GHz, allowed to demonstrate the corresponding 1-Hz defined NETD of 0.86 K and 2 K in a focused measurement setup with a cavity black-body standard chopped mechanically at 1.5 kHz. With a simultaneous dual-channel operation, the NETD scaled down to 0.64 K, indicating near-zero noise correlation between both polarization paths.

The number of environment-detecting sensors inside cars continuously increases, to enable failsafe autonomous driving. With more sensors, the probability of performance degrading interferences increases. A promising solution to the interferences is orthogonal frequency division multiplex (OFDM) radar. Due to the complex modulation scheme, the analog front end, especially the power amplifier in the transmitter, has to deal with a high peak-to-average power ratio. Therefore, conventional amplifiers have to be operated in power back-off to maintain linear operation at the drawback of reduced power-added efficiency. To mitigate this problem, a Doherty power amplifier for an automotive radar transceiver is proposed. In this work, we present a design methodology for an integrated Doherty amplifier for automotive radar applications, focussing on the theory of operation by analyzing transistor-level simulations. Small- and large signal simulations analyze the concept of load modulation for a Doherty amplifier in the automotive frequency band from 76--81 GHz. Using a fully differential transmission-line-based approach, we showcase the superior performance of an automotive Doherty amplifier over an conventional state-of-the-art reference amplifier. In measurements, the proposed Doherty amplifier achieves a saturated output power of 17.2 dBm with a peak power-added efficiency of 11.6%. When operating in 6 dB back-off, the PAE still amounts to 6.1%. Thereby we propose to improve conventional automotive power amplifiers by incorporating them into a Doherty amplifier.

The design complexity of high-speed and power-efficient circuits increases to higher operation frequencies. Therefore, this manuscript gives an overview of how to design and optimize fully differential emitter-coupled logic (ECL) gates using two dual-modulus prescalers with switchable division ratios of 4 and 5. The first prescaler is optimized to the highest operation frequencies, up to 142 GHz and even 166 GHz for the division ratios of 5 and 4, respectively. Furthermore, another prescaler has been optimized for the widely used 80 GHz band, which has been heavily promoted by the automotive industry and has a high number of components in that domain. Both prescalers can be utilized in a fully programmable frequency divider with a wide division ratio range. As the measurement of the additive phase noise for frequency-converting devices with excellent noise performance is quite challenging, this is discussed theoretically and carried out practically. The measured jitter is between 500 as and 1.9 fs within integration limits of 100 Hz up to 1 MHz offset frequency.

In this contribution, the simulation and measurement results of a 4/5 dual-modulus prescaler, operating from dc to 142 GHz with a power consumption of 144 mW, are presented. For a division ratio of 4, the maximum operation frequency of 166 GHz is even higher. The prescaler is the core of a fully programmable dual-modulus frequency divider, which is a crucial component of modern measurement systems. The effect of the physical lengths and the resulting internal delays on the prescaler’s performance is analyzed. Furthermore, the voltage level of the fully differential emitter-coupled logic (ECL) is optimized in terms of phase noise and maximum operating frequency. The monolithic microwave integrated circuit (MMIC) is realized in a 130-nm SiGe:C BiCMOS technology with $f\textsubscript{ \emph T}$ / $f\textsubscript{max}$ $=$ 470/650 GHz.

This work presents a static divide-by-16 in a 130-nm SiGe-BiCMOS technology, aiming to demonstrate the technologies’ potential. A bias network followed by four divide-by-2 stages and an output buffer is designed. The DC power consumption of the first divider stage and the four divider flip flops in static current mode logic (CML) with buffer is 134.3 mW and 396 mW, respectively. The maximum input frequency of the divider is 163 GHz. The corresponding necessary input power at the divider’s bias network is 4.39 dBm. The observed self-oscillating frequency is 110.56 GHz, while the output power at the by-16 output of the divider is around -9 dBm. Moreover, a special focus is set on the accuracy of divider simulations and the influence of parasitic elements compared to measurement results.

Radar systems are gaining in popularity and spreading into more and more applications due to their robust measurement method. While single-chip solutions have been published in the last decade in the upper millimetre-wave range, solutions are still very limited in the lower THz range. In this paper, a 0.48 THz FMCW-radar transceiver MMIC in a 130 nm silicon-germanium (SiGe) technology is presented. The MMIC consists of one Tx and Rx channel, respectively. The components for frequency synthesis and on-chip patch antennas are fully integrated into the MMIC. The achievable tuning range of the MMIC is 0.448 - 0.491 THz with a peak on-chip output power of about -9.4 dBm. The MMIC was designed and manufactured with the IHP SG13G3 technoloay,

A very detailed investigation of high-speed silicon–germanium (SiGe) heterojunction bipolar transistors (HBTs) showed an underestimation of the measured peak cutoff frequency by simulations with a hydrodynamic (HD) model. It was speculated that this might be due to a breakdown of the HD approximation or unknown additional mechanical stress. We repeated those simulations with the more fundamental Boltzmann transport equation (BTE) based on the same device model (doping profiles, 2-D geometry, parasitics, and so on) and obtained almost similar results showing that this failure was not due to a breakdown of the HD approximation. Since additional uniaxial stress along the direction of the lateral base has been shown to increase the cutoff frequency, we investigated this effect. We found by 2-D device simulations that the increase in the peak cutoff frequency is rather small, and at high stress levels, it even decreases, if the uniaxial stress is applied homogenously. This is due to the reduction of the conductivity of the highly doped collector layer by the stress. If the stress is limited to the intrinsic transistor, the increase in the cutoff frequency is monotonic with growing stress. On the other hand, the collector current for a given base–emitter voltage also increases with stress leading to an overestimation of the collector current compared with the measurements. If this increase is corrected by a slight decrease in the germanium profile, the gain in the peak cutoff frequency is lost. Thus, the underestimation of the peak cutoff frequency cannot be explained by an additional homogeneous uniaxial stress in the intrinsic transistor.