Muhammad Imran

Deep Neural Networks (DNNs) have achieved out standing performance in various fields. However, as DNNs continue to grow in size, their performance is hindered by the memory wall problem, where data memory bandwidth becomes a bottleneck. Resistive Random Access Memory (ReRAM)-based DNN accelerators offer promising solutions to this challenge, enhancing data processing efficiency. However, these architectures face reliability issues due to cell immaturity, notably device conductance variation and offset currents in High Resistance State (HRS) cells, which compromise DNN accuracy and processing performance. This paper addresses the reliability issues of the ReRAM-based computing-in-memory (CIM) accelerator. In particular, this paper introduces a novel design methodology of shared-exponent deployment on the accelerator, enhancing variation tolerance through fine-grained quantization. In addition, this paper proposes a variation-resilient data encoding to further improve the robustness in combination with the proposed design and introduces a programming scheme for the offset current compensation. Experimental results conducted on various DNN models and datasets reveal that the proposed techniques outperform existing methods in variation tolerance and significantly improves performance and energy efficiency compared to the conventional baseline, even under high variation environments.

Approximate Computing (AC) is a promising computing paradigm that provides efficiency and speed while maintaining acceptable accuracy in error-tolerant applications. However, most of the existing AC designs are prone to Hardware Trojan (HT) attacks. Moreover, the existing HT mitigation techniques have been designed for exact systems and due to the architectural differences in the approximate systems, these conventional mitigation techniques have limited efficacy when used in the context of AC. Therefore, this paper presents two novel methods, named Partial Comparison (PC) and Hybrid Comparison (HC), that effectively mitigate HTs in approximate systems while achieving a 30% and 55% improvement in the area and the power efficiency, compared to the existing state-of-the-art technique. PC focuses on LSBs while HC considers both LSBs and MSBs for HT masking. The effectiveness of proposed techniques is validated through a practical case study of image processing; three IPs with different HTs are successfully masked with a PSNR and SSIM of 33dB and 0.92 respectively. In conclusion, this research provides practical solution to enhance security and reliability of approximate systems with optimal performance benefits.

In-memory Computing (IMC) using Phase Change Memory (PCM) has proven to be effective for efficient processing of Deep Neural Networks (DNNs). However, with the use of multi-level cell PCM (MLC-PCM) in NVMs-based accelerators, errors due to resistance drift in MLC-PCM can severely degrade the DNNs accuracy. In this paper, an analysis of the impact of resistance drift errors on accuracy of MLC-PCM based DNN accelerator shows that the drift errors alone can significantly impact the accuracy. This paper proposes Hydra, which is a hybrid resistance drift resilient architecture for MLC-PCM based DNN accelerators which use IMC for efficient computations. Hydra utilizes Tri-level cell PCM, which has a negligible resistance drift error rate, to store the critical bits of DNNs parameters and MLC-PCM (4-level cell), which has a higher error rate (but offers more storage density), for the non-critical bits. Experimental results on various DNN architectures, configurations and datasets show that, with the presence of resistance drift errors in PCM, Hydra can maintain the baseline accuracy of DNNs for up to 1 year (resistance drift is time-dependent), whereas conventional drift tolerance techniques lead to a significant accuracy drop in just a few seconds.

Deep Neural Networks (DNNs) have emerged as the most effective programming paradigm for computer vision and natural language processing applications. With the rapid development of DNNs, efficient hardware architectures for deploying DNN-based applications on edge devices have been extensively studied. Emerging Non-Volatile Memories (NVMs), with their better scalability, non-volatility and good read performance, are found to be promising candidates for deploying DNNs. However, despite the promise, emerging NVMs often suffer from reliability issues such as stuck-at faults, which decrease the chip yield/memory lifetime and severely impact the accuracy of DNNs. A stuck-at cell can be read but not reprogrammed, thus, stuck-at faults in NVMs may or may not result in errors depending on the data to be stored. By reducing the number of errors caused by stuck-at faults, the reliability of a DNN-based system can be enhanced. This paper proposes CRAFT, i.e., Criticality-Aware Fault-Tolerance Enhancement Techniques to enhance the reliability of NVM-based DNNs in the presence of stuck-at faults. A data block remapping technique is used to reduce the impact of stuck-at faults on DNNs accuracy. Additionally, by performing bit-level criticality analysis on various DNNs, the critical-bit positions in network parameters that can significantly impact the accuracy are identified. Based on this analysis, we propose an encoding method which effectively swaps the critical bit positions with that of non-critical bits when more errors (due to stuck-at faults) are present in the critical bits. Experiments of CRAFT architecture with various DNN models indicate that the robustness of a DNN against stuck-at faults can be enhanced by up to 105 times on CIFAR-10 dataset and up to 29 times on ImageNet dataset with only a minimal amount of storage overhead i.e., 1.17%. Being orthogonal, CRAFT can be integrated with existing fault-tolerance schemes to further enhance the robustness of DNNs against stuck-at faults in NVMs.

Phase Change Memory (PCM), with its better scaling potential compared to DRAM, is seen as a promising candidate to replace or complement DRAM. The heat generated from a RESET programming pulse to a PCM cell can disturb the neighboring cells which are not being programmed. Write disturbance (WD) poses a critical reliability challenge in high-density PCM memory with scaling below 20nm process technology node. Increasing the intra-cell space can eliminate the WD, however, it reduces the storage density which counteracts the benefits of scalability in PCM. At architectural level, a verify and correct (VnC) technique can be used to address this problem. However, this leads to an increased number of write operations, thus degrading performance, energy efficiency and memory lifetime. Due to its dependence on the type of programming operation and the state of the neighboring cell, WD is a data-dependent problem. Exploiting this property, encoding techniques have been proposed to reduce the frequency of WD-vulnerable data patterns. These techniques, however, do not eliminate the WD in an array and ultimately rely on the VnC method to ensure reliable memory operation. This article introduces a novel architecture, based on encoding and multi-level programming characteristics of PCM, to eliminate the intra-array WD in PCM. By eliminating WD and hence the need for a VnC operation, the proposed architecture improves performance, energy efficiency and memory lifetime. Our evaluation of the proposed architecture shows an average reduction of 57 percent in the number of writes (to service one write request) over the existing state-of-the-art intra-array WD-mitigation technique. Depending on the PCM write bandwidth, the proposed architecture can reduce the write service time by up to 27 percent, on average, compared to the existing best-performing technique. This leads to an average improvement of 15 percent in IPC. Additionally, by eliminating the overhead of a verify operation, the write energy efficiency is also improved by 8 percent over the previous art. Finally, with an average reduction of 26 percent in bit flips, the proposed method also improves the memory lifetime. The proposed method is also proven to be effective when considering WD both within the word-lines and across the bit-lines.

Phase change memory (PCM) is an emerging, resistance-based, nonvolatile memory. With a promising scaling potential, PCM can replace the existing charge-based memory technologies. A highly scaled PCM is prone to write disturbance (WD) because of a high-current RESET programming pulse. Exploiting the data-dependent nature of WD, encoding techniques have been proposed to reduce the frequency of WD-vulnerable data patterns. These techniques work along with a verify and correct (VnC) method to ensure memory reliability. However, the effectiveness of these techniques varies depending on the data patterns. Unlike the conventional methods, this article introduces a WD-aware programming technique to mitigate WD in PCM. The proposed method encodes the data based on the number of WD-vulnerable cells and the bit flips. By reducing the number of WD-vulnerable cells as well as the bit flips, the proposed method is more effective than the existing encoding techniques, in mitigating WD as well as improving the memory lifetime. Evaluation using various realistic workloads shows that the proposed method can reduce the average word-line WD errors by 62%, compared to the existing state of the art. With a reduced number of WD errors, the frequency of a VnC operation is also reduced. This leads to a reduction of 44% in the number of extra writes and 20% in the average write time. With reduction in the number of writes and the write time, instructions-per-cycle is improved by 9% and the write energy by 11% over the existing art. By reducing the number of bit flips compared to the previous state of the art, the proposed method improves the PCM memory lifetime by 13% to 33%, considering the asymmetry of SET and RESET operations in impacting the cell endurance.

Clock network plays the most significant role in power consumption in IC design. Since a clock network normally has a high switching ratio, power optimization of the clock network is one of the best solutions to minimize dynamic power and total power in modern IC designs. The clock network is synthesized based on an initial flip-flop placement. The number of clock buffers and their sizes are decided by the initial placement. Moreover, clock wires, which are the major sources of clock power consumption, are also constructed based on the flip-flop placement. As a result, the flip-flop placement determines the quality of the clock network. In this article, we propose a new clock network optimization method to reduce the dynamic power consumption of clock network. The method first creates virtual tiles over the entire design area and selects the most effective columns to align flip-flops in lines. Once the effective columns are determined, flip-flops are relocated based on the virtual tiles in the columns considering the minimum moving distance. By aligning flip-flops, it is possible to significantly reduce both wire capacitance and wire length. Since it does not change the clock structure, unlike the conventional clock network optimization techniques which use multibit flip-flop or register bank, there is no degradation in timing or other constraints. Experimental results show that the proposed method reduces the wire capacitance, wire length, and via count up to 23.2%, 10.2%, and 16.4%, respectively, in five industrial intellectual property (IP) designs. The reduction in clock network power is 14.1% on average.

With the scaling limitations and increasing leakage power of the existing charge-based memories, next-generation memory technologies to overcome the issues are in development. Among the various emerging memories, Phase Change Memory (PCM) is considered as a promising candidate due to its scalability potential and negligible leakage power. For enhanced storage density, the multi-level cell (MLC) operation has been proposed for PCM. This, however, comes at cost of poor reliability, write energy increase and performance degradation. Unlike DRAM, the MLC PCM has a much higher soft error rate due to the resistance drift phenomenon. Error correction code (ECC) schemes can be utilized to improve the MLC PCM reliability, however, this would lead to a lower storage density and an increase in write energy and latency. The iterative programming required for the MLC PCM also degrades its energy efficiency and performance. This paper introduces a simple yet effective encoding scheme to mitigate the problems of the MLC PCM. By using a simple XOR-based encoding, the proposed architecture minimizes the most drift-prone state in the data. The method divides the original data into several encoding blocks and analyzes initial pattern frequencies for each 2-bit pattern. Based on the initial pattern frequencies, the inputs for the XOR encoding are selected that result in minimal frequency of the drift-prone state. This considerably enhances the MLC PCM reliability, leading to a high storage density with a reduced ECC overhead. The energy efficiency and performance are also improved due to reduction in iterative current pulses and ECC overhead. Simulation results show a reduction of about 105X in soft error rate. The improvements in energy efficiency and performance over the conventional 4-level cell (4LC) PCM are 11.5% and 31.9%, respectively.