Zhiyu Wang

This article demonstrated the design and fabrication of a compact software-defined RF (SDR) microsystem based on heterogeneous integrated (HI) RF transceiver and baseband chiplets. To achieve this microsystem, we propose a silicon substrate process with through silicon vias (TSVs) and multiredistribution layers (RDLs) on both surfaces. Three RDLs with $10~\mu $ m linewidth and $10~\mu $ m line gap are achieved with silicon oxide dielectrics, which can support complex and high-density pin interconnections among chiplets. And by introducing a silicon-embedded metal layer and thick polyimide (PI) dielectric layer between thick metal layers, four RDLs with large metal cross sections and high overcurrent capacities are realized to support low loss RF transmission lines (TLs) and high DC power redistribution. Based on the HI process, a $30\times 30\times 2$ mm compact SDR microsystem is realized by integrating two dual-RF-channel transceiver dies and one field-programmable gate array (FPGA) die, which approaches four independent 100 MHz–2.7 GHz broadband RF channels. The transmitter shows measured maximum gain of 3.3dB and output 1 dB compression (OP1dB) of 6.7dBm at 1.5GHz. The receiver shows measured maximum gain of 53.4dB and noise figure (NF) of 5.1dB.

In this article, we experimentally decouple the effects of parasitic capacitance and process-induced current collapse on the RF power-added efficiency (PAE) of $0.25~\mu $ m gallium nitride (GaN)-on-SiC high-electron-mobility transistors (HEMTs) by systematically varying the source-connected field-plate (FP) length. In a standard process with high-surface-trap density, current collapse dominates at 10–18 GHz, and longer FPs yield higher PAE. After process optimization that reduces the interface trap density, the dominant limitation shifts: parasitic output capacitance outweighs collapse, and PAE improves with shorter FPs at both X- and Ku-bands. These results reveal a clear transition from collapse-limited to capacitance-limited efficiency and establish a practical design guideline for FP engineering in millimeter-wave GaN HEMTs.

This paper investigates the power pattern synthesis of arbitrary planar arrays with fixed element layouts and variable excitation. The synthesis problem is formulated as a weighted nonlinear least-squares (WNLS) objective to minimize deviations from target power levels or mask bounds. Through gradient analysis, we derive global-optimality conditions that shift the focus from solving for excitation to solving for the target electric field. By embedding the fitness into gradient equations via eigenvalue decomposition, the problem reduces to a fourth-order tensor eigenpair problem. It is proven that all local optima lie on tensor eigenpairs and the global optimum corresponds to the smallest real eigenvalue. Based on this derivation, we propose a novel, general method “TP-GN”, which uses the tensor power (TP) method for the outer iterations and the Gauss-Newton (GN) method for the inner steps. By applying inverse power iterations from an ideal pattern, TP-GN rapidly approaches the global optimum for arrays with fixed geometries. This property also allows for estimating the minimum source size necessary to achieve synthesis goals. Furthermore, we present a logarithmic scale approximation strategy, report empirical computational complexity, and discuss tolerance selection and initialization strategies in detail. Numerical results demonstrate the method’s superior performance, flexibility, rapid convergence, robustness, and applicability to large array synthesis. Experiments confirm that truncated TP-GN efficiently handles mask-constrained problems and when the mask is infeasible, TP-GN converges to a best-compromise solution.

In this letter, a high-power three-stage monolithic microwave integrated circuit (MMIC) reflective limiter based on GaAs PIN diodes is presented. The optimized power division and PIN diode structure ensure uniform power and thermal distribution, effectively mitigating the formation of hot spots and thereby enhancing the reliability of the limiter. Consequently, the limiter operates stably under high-power continuous-wave (CW) conditions. Within the frequency range of 13.5–17.5 GHz, the limiter can withstand an incident power of up to 50 W (47dBm) in continuous wave mode, while maintaining an output power below 16.3 dBm (42.7 mW). The insertion loss is less than 1.5dB, and the return loss is better than 12.6 dB. Additionally, the proposed limiter features a compact chip size of only 2.2mm². The reliability testing results demonstrate that the limiter can operate stably under high-power CW conditions without noticeable performance degradation.

This paper presents a 6-bit active vector modulator phase shifter (VMPS) operating from 2 to 20 GHz for phased array communications. The PS integrates a three-stage in-phase/quadrature (I/Q) signal generation based on the proposed Lattice-Ladder topology to enhance the required electromagnetic coupling, 7-bit variable gain amplifier (VGA) cells, and a compact passive matching network. The theoretical analysis for the Lattice-Ladder based I/Q configuration is formulated through even-odd mode analysis and [ABCD] matrix derivation. The proposed 6-bit PS is designed and fabricated in 0.13 μm bulk CMOS. The measured results reveal an insertion loss of 1 ~ 4.7 dB, a phase root-mean-square (RMS) error of 0.8° ~ 2.4°, and amplitude RMS error of 0.37 ~ 0.63 dB. The chip occupies an area of 1.47 x 0.9 mm2 and consumes 17.16 mW DC power. The proposed structure can be a good candidate for future phased array radars and satellite communications.

Pre-sampling multiplying digital-to-analog converters (MDACs) feature high speed and energy efficiency. However, the parasitic capacitance between the sampling capacitor and the reference capacitor in the pre-sampling MDAC can induce gain and intercept errors in the pipeline stage, which significantly degrades the linearity of the entire pipelined ADC. This work presents a pre-sampling MDAC with parasitic compensation using a split-capacitor technique in the analog domain, combined with an intercept calibration method to correct the gain and intercept errors. Employing this technique, a 12-bit pre-sampling pipelined ADC fabricated in a 28nm CMOS process consumes 495mW at a 10GS/s sampling rate, achieving a signal-to-noise-and-distortion ratio (SNDR) of 50.8dB and a spurious-free dynamic range (SFDR) of 60.7dB with a Nyquist input signal.

In this letter, a Ka-band band-stop filter (BSF) with stub-loaded multimode resonators is presented and analyzed. Each resonator consists of a split ring resonator with a centrally loaded short stub. Through the application of odd–even mode theory and admittance network analysis, the influence of the coupled stubs on the performance of individual resonators and the coupling response among multiple resonators are elucidated, which enables easily controllable stopband responses. Furthermore, the overall size of the filter is significantly reduced and coupling is enhanced by adopting folded feedlines. The BSF is realized by GaAs integrated passive device (IPD) technology. Experimental results indicate that the filter demonstrates sharp attenuation slope and high attenuation level (AL), along with favorable passband insertion loss and compact sizes.

Whether in analog or digital phased arrays, the predominant factor contributing to beam pointing deviation, particularly in extensive angle scanning scenarios, is the anisotropy of antenna elements. This paper presents an efficient beam pointing correction method for uniform planar phased arrays with anisotropic elements. Based on the gradient analysis of the radiation pattern, this method establish a transcendental equation which buildup the relation between the desired beam pointing and the real beam pointing. Newton’s iteration algorithm is utilized to solve the problem, and two iterative initial values are thoroughly discussed and integrated within this algorithm for fast convergence. Additionally, the paper verifies the presented method with both simulation and measurement of an 8×8 phased array. Simulations validate applicability at center and edge frequencies, yielding beam pointing errors below 0.7°. At the center frequency, arrays from 4×4 to 16×16 exhibit pointing errors below 0.75°. Compared with the conventional EEP method, the proposed approach provides superior pointing correction. Experiments confirm that for scan angles above 30° the pointing error is reduced by over 60% despite other error sources.

Brewster effect originally refers to the reflectionless transmission of a TM-polarized wave impinging on a lossless dielectric surface at a particular angle. It is generally thought that either the introduction of loss or the change of polarization will break the reflectionless phenomenon. Here, we derive an analytical solution for achieving the generalized Brewster effect in highly dissipative anisotropic media for both TE- and TM-polarized waves. Based on the composite electric and magnetic resonator, we designed a three-dimensional metasurface with controllable Brewster angles to absorb dual-polarized incident waves without reflection. By stacking massive different metasurface units, each with a deliberately designed Brewster angle, it is possible to achieve omnidirectionally matched absorption for dual-polarized incident waves from a given source. As a proof of concept, we implemented an inhomogeneous planar metasurface. Each unit of this metasurface has a Brewster angle precisely adjusted according to a given line source, which is used to absorb the corresponding impinging wave without reflection. Both full-wave simulations and experimental measurements confirm the nearly omnidirectionally matched absorption. Our work offers a promising approach for applications of metasurfaces in electromagnetic shielding, compatibility, and microwave measurements.