Saravanan Yuvaraja

High-temperature Ohmic contact annealing is universally required in aluminum nitride (AlN) power device fabrication, yet its impact on adjacent AlN surfaces subsequently used for Schottky contact formation has never been investigated. We show that the Ohmic metal stack in combination with 950 °C rapid thermal processing markedly roughens the adjacent AlN surface, increasing the root mean square roughness from below 0.5 nm to approximately 2 nm and rendering AlN Schottky barrier diodes non-rectifying. This degradation is absent when the same thermal budget is applied without the metal stack, identifying that the thermal budget alone is not the causal factor. Cross-sectional scanning transmission electron microscopy and energy-dispersive x-ray spectroscopy reveal AlOx- and Al-N-O-related interfacial layers formed at the Schottky contact region as a direct consequence of this annealing process. Sequential pretreatment by buffered oxide etching and atomic layer etching removes these layers, reduces the surface roughness to 0.3 nm, and recovers near-ideal Schottky characteristics with an ideality factor of 1.36. Temperature-dependent reverse current–voltage and multifrequency conductance analyses identify trap-assisted tunneling as the dominant reverse leakage mechanism. These findings uncover a previously unrecognized process-coupling effect between high-temperature Ohmic contact annealing and subsequent Schottky interface formation in AlN power device fabrication and provide a practical surface recovery route toward reliable rectifying contacts.

In this work, enhancement-mode p-MOSFETs on p-GaN/AlGaN/GaN-on-Si substrates were fabricated using a gate recess process that combines reactive ion etching (RIE) with atomic layer etching (ALE), where ALE is employed as an interface engineering approach following conventional plasma etching to mitigate recess-induced interface damage. Compared with RIE-only devices, the RIE + ALE devices yield smoother surfaces and significantly suppress interface trap density. These interface improvements lead to enhanced subthreshold characteristics and markedly tighter device-to-device uniformity. In particular, the subthreshold swing decreased from 365 ± 179 to 149 ± 17 mV/dec, while the off-state leakage current was suppressed from 1.9 ± 3.6 × 10−7 to 8.5 ± 5.5 × 10−9 mA/mm. These results demonstrate that ALE provides an effective interface engineering approach for suppressing interface damage and enabling uniform enhancement-mode p-MOSFETs, highlighting its potential for reliable GaN complementary metal–oxide–semiconductor logic and power integrated circuits.

Reliable engineering of low-resistance metal semiconductor (M/S) contacts is critical for advancing indium oxide (In2O3) based semiconductor technologies. As device dimensions shrink to the micrometer regime, minimizing contact resistance becomes essential to ensure channel limited operation rather than contact dominated. In this study, we systematically optimized Ni/In2O3 contacts using mild rapid thermal annealing (RTA) at 250 °C in nitrogen ambient conditions compatible with back-end-of-line (BEOL) processing and evaluated their performance using the transfer line method (TLM). Ni/In2O3 TLM structures were fabricated via photolithography and liftoff, followed by RTA at varying durations. Quantitative TLM analysis demonstrated a substantial reduction in contact resistance (RC) to 6.24 Ω, normalized contact resistance (N · RC) to 1.25×10−1 Ω cm, specific contact resistivity (ρC) to 1.53×10−6 Ω cm2, and a short transfer length (LT) of 123 nm, all achieved without intentional doping or complex metallization. This process driven, BEOL compatible approach provides a robust route to low-resistance contacts in In2O3 thin films, enabling a reliable foundation for next generation low power, high performance oxide electronics.

The development of low-power computing sectors requires compact, power-efficient and high-performance integrated circuits. Hybrid technology that combines n-type metal oxide thin-film transistors and p-type organic thin-film transistors offers a potential solution. However, increasing the transistor density of these systems through vertical stacking is challenging due to issues related to thermal budget and interface roughness. Here we report a six-stack hybrid complementary transistor technology that has 41 layers and uses n-type indium oxide (In ₂ O ₃ ) and a p-type organic semiconductor (C16IDT-BT) as channel materials. We test 600 transistors and show that n-type oxide devices and p-type organic devices exhibit comparable field-effect mobilities and saturation currents. We also create 300 hybrid inverters by integrating the oxide and organic transistors; the circuits exhibit a gain of 94.84 V V ⁻¹ and a power consumption of 0.47 µW. We also fabricate NAND and NOR gates comprising transistors from four stacks. Thermal stability analysis shows that device characteristics begin to degrade above 50 °C, a known limitation of low-thermal-budget processes. Such performance is sufficient for many large-area electronics applications, but further thermal optimization will be necessary to extend operational robustness towards standard industrial conditions.

Beta Gallium Oxide (β-Ga2O3) Junction Barrier Schottky diodes possess excellent breakdown characteristics and efficiency, but the lack of p-type β-Ga2O3 has led to the use of alternative materials, such as NiOx, which pose challenges regarding lattice mismatch and temperature stability. This work reports a unipolar β-Ga2O3 diode enabled by the magnesium (Mg) diffusion process to create high-resistance electron-blocking regions. The Mg diffusion process developed in this work uses a room temperature compatible chemical process followed by an 800 °C annealing step, which is lower compared to already reported methods in the literature. Therefore, the proposed method is thought to reduce the device processing temperature budget and hence cost. The resulting device achieves an Ion/Ioff ratio of ∼109, a knee voltage of ∼0.9 V, and a breakdown voltage of 596 V. In addition, it demonstrates stable operation from 100 to 500 K, highlighting its suitability for electronics operating across a broad temperature range.

This study demonstrates the high-temperature operation of AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) based on nickel oxide (NiOx) as an intermediate gate oxide, achieving stable performance up to 400 °C. Compared to the control sample with only an SiNx gate dielectric, the proposed device exhibited significant improvements: (1) enhanced thermally induced VTH stability, (2) a flat transconductance (gm) curve indicating improved linearity, and (3) lower and stable drain-to-source saturation voltage (VDS,sat). Notably, the ΔVTH shift for D-mode MIS-HEMT with NiOx was effectively reduced to ∼+0.4 V, compared to ∼−1.4 V in the control sample, over a temperature range from 25 to 400 °C. This improvement is attributed to hole carrier generation in the NiOx layer, which increases the depletion region and stabilizes the stored charge underneath the gate at high temperatures. This work demonstrates that the NiOx gate oxide layer significantly enhances VTH stability and linearity in GaN MIS-HEMT, ensuring reliable and stable device operation at high temperatures.

Two-dimensional materials are increasingly integral to beyond-CMOS electronics, facilitating the development of emerging memristive device technology for information storage and neuromorphic computing. Despite their emergence, some critical challenges including low device yield, substantial device-to-device (D2D), and cycle-to-cycle (C2C) variability factors hinder the development of high-density memristive devices for future low-power electronic applications. Here, we demonstrate a memristive crossbar array (MCA) in which multilayer 2D MoS₂ acts as a resistive switching layer that offers lower switching voltages with a few microseconds pulse width. Additionally, the use of 2D MoS₂ further excels in integration density and energy efficiency, which significantly helps to achieve a device yield of 94%. Moreover, the 2D MoS₂ controlled growth process ensures the uniformity of MoS₂ layers across a (10 × 10) crossbar array that enhances the stability of fabricated MCA's having minimal variability in device switching voltages (V_SET: 4.16% and V_RESET: 3.60%). The fabricated devices show excellent endurance (∼24,000 cycles) and retention (1.6 × 10⁶ s). Furthermore, due to lower switching voltages and fast switching speed, the fabricated devices consume 53 pW power and 53 aJ energy, making them more energy-efficient and achieving an impressive 97.79% accuracy in MNIST digit recognition through synaptic behavior simulation.