Pavel Kustarev

Reference-based Super-Resolution (RefSR) aims to restore a low-resolution image by transferring real textures from a high-resolution reference of similar content, rather than hallucinating missing details as in single-image super-resolution. Most existing RefSR methods decompose the problem into separate matching, alignment, and fusion stages, implemented as sequentially trained modules. This decomposition causes errors to accumulate across stages and imposes inductive biases that limit what the model can learn from data. Instead, we propose to handle correspondence and texture transfer jointly through a single attention operation. We propose an end-to-end transformer that operates on the concatenated sequence of input and reference tokens, with self-attention implicitly performing both matching and texture transfer. The architecture introduces binocular 2D Rotary Positional Embedding, a shared coordinate frame for input and reference patches, and a resolution-adaptive attention scaling scheme in which the logits are rescaled by the length of the processed sequence, allowing the model to operate at resolutions beyond those seen at training time. On the standard CUFED5 and WR-SR benchmarks under bicubic ×4 downsampling, our method improves over the best previously published RefSR approach by 0.33 dB Peak Signal-to-Noise Ratio (PSNR) on CUFED5 and, for the first time, surpasses strong single-image super-resolution models on WR-SR by 0.29 dB PSNR. Unlike multi-stage pipelines, the proposed model is end-to-end trainable and requires no pretrained components, showing that a single attention operation over the joint token sequence is sufficient for RefSR. The approach is broadly applicable to image restoration settings where a highresolution reference of similar content is available.

This article discusses the problem of choosing the optimal description level when designing digital circuits in HardwareDescription Language (HDL). The relevance of this research is due to the fact that manual optimization of designto improve its characteristics often conflicts with maintaining readability, configurability, and tight developmentdeadlines. At the same time, the constructs, idioms, and practices of abstract (behavioral) hardware description offeredby modern HDLs are supported by optimizing logic synthesizers in modern CAD systems for Field-ProgrammableGate Array (FPGA) with varying levels of quality. Existing sets of evaluation tests (benchmarks) often focus onintegrated performance indicators, preventing a detailed assessment of the effectiveness of specific code transformationmechanisms. The main goal of this work is to conduct a comparative analysis of modern FPGA CAD systems and createa set of recommendations for the effective use of HDL without compromising the quality of synthesized solutions.The research is conducted in several stages. The first stage involves classification of known optimization methodsused in the transformation of Verilog/SystemVerilog-designs into a structural representation. Based on the resultingclassification, synthetic tests are developed to verify optimizations, related to specific classes. These tests consist ofpairs of behaviorally equivalent designs, one of which is optimized manually, while the other has redundancy due to theuse of abstract or inflated Verilog/SystemVerilog language constructs and/or behavior description patterns. The “gap”in the characteristics of these implementations allows us to draw conclusions about the level of CAD efficiency in theapplication of specific optimizations. A three-level classification of optimizations of behavioral descriptions of hardwareis proposed. Within the framework of this classification, a test package of 19 tests has been developed, selectively aimedat evaluating optimizations belonging to different levels of the proposed classification. These tests have been applied toa number of modern FPGA CAD systems (Vivado, Quartus, Yosys). A consistent decrease in the effectiveness of codingpatterns is demonstrated as they approach the behavioral level of description, with the differences between differentCAD systems increasing as the level increases. A significant drop in quality of results is observed when evaluatingbehavior optimization at the level of multiple clock cycles. Based on the results obtained, practical recommendations areformulated for developers of digital equipment on the style of writing HDL code, allowing the most effective use of thecapabilities of specific synthesizers. The results of the work allow us to identify the common “core” of HDL and logicdescription patterns without compromising the quality of the synthesized equipment as well as to determine promisingdirections for further improvement of synthesizers and HDL.

This article is devoted to digital image processing algorithms, namely, super-resolution task. Currently, various methods of image restoration based on deep learning are actively developing. These methods are used to solve image restoration problems, such as inpainting, denoising, and super-resolution. One important class of super-resolution methods is reference-based super-resolution that allows restoring the missing information in the main image using reference images. Methods of this class are mainly represented by convolutional neural networks which are widely used in computer vision problems. Despite the significant achievements of existing methods, they have one significant drawback: the image area not represented in the reference image often has worse quality compared to the rest of the image, which is clearly visible to the observer. In addition to convolutional neural networks, diffusion models are actively used in image restoration problems. They are capable of generating images with high quality and diverse fine details but suffer from a lack of fidelity between the generated details and the real ones. The aim of this work is to improve the quality of the reference-based image restoration method using the diffusion model. A hybrid architecture of the diffusion model denoising neural network is proposed consisting of three main blocks: the basic denoising module, the reference-based module, and the fusion module for the final result generation. Three models were trained: a diffusion model, a referencebased convolutional neural network, and a proposed hybrid model. All three models were trained and evaluated on the Large-Scale Multi-Reference Dataset dataset. Based on the results of the trained models testing, a qualitative (visual) and quantitative comparison of the three models was done. The hybrid model demonstrated higher image quality, clarity, and consistency compared to the convolutional neural network using references and better restoration of real details compared to the diffusion model. According to the quantitative evaluation, the hybrid model also showed higher results compared to pure models. The results of this work can be used to increase the resolution of any images using reference information.

Dynamic blockage of radio propagation paths between the user equipment (UE) and the 5G New Radio (NR) Base Station (BS) induces abrupt rate fluctuations that may lead to sub-optimal performance of the Transmission Control Protocol (TCP) protocol. In this work, we characterize the effects of dynamic human blockage on TCP throughput at the 5G NR air interface. To this aim, we develop an analytical model that expresses the TCP throughput as a function of the round-trip time (RTT), environmental, and radio system parameters. Our results indicate that the blockage affects TCP throughput only when the RTT is comparable to the blocked and non-blocked state durations when the frequency of state changes is high. However, such conditions are not typical for dynamic body blockage environments allowing TCP to benefit from the high bandwidth of 5G NR systems fully.

Licensed assisted access (LAA) enables the coexistence of LTE and Wi-Fi in unlicensed bands, while potentially offering improved coverage and data rates. However, cooperation with the conventional random-access protocols that employ listen-before-talk (LBT) considerations makes meeting the LTE performance requirements difficult, since delay and throughput guarantees should be delivered. In this paper, we propose a novel channel sharing mechanism for the LAA system that is capable of simultaneously providing the fairness of resource allocation across the competing LTE and Wi-Fi sessions as well as satisfying the quality-of-service (QoS) guarantees of the LTE sessions in terms of their upper delay bound and throughput. Our proposal is based on two key mechanisms: (i) LAA connection admission control (CAC) for the LTE sessions and (ii) adaptive duty cycle resource division. The only external information necessary for its operation is the current number of active Wi-Fi sessions inferred by monitoring the shared channel. In the proposed scheme, LAA-enabled LTE base station fully controls the shared environment by dynamically adjusting the time allocations for both Wi-Fi and LTE technologies, while only admitting those LTE connections that should not interfere with Wi-Fi more than another Wi-Fi access point operating on the same channel would. To characterize the key performance trade-offs pertaining to the proposed operation, we develop a new analytical model. We then comprehensively investigate the performance of the developed channel sharing mechanism by confirming that it allows to achieve a high degree of fairness between the LTE and Wi-Fi connections as well as provides guarantees in terms of upper delay bound and throughput for the admitted LTE sessions. We also demonstrate that our scheme outperforms a typical LBTbased LAA implementation.

The need of rapid design space exploration, early prototype construction and high level of reuse of technical decisions about microarchitecture in hardware design field actualize development of technologies based on custom user-specified hardware generation. However, existing approaches and tools typically offer configurability at the level of predefined set of parameters. In the article, the concept of framework architecture based on Micro-Language IP (MLIP) cores is presented. This approach facilitates creation of lightweight hardware description languages adapted to specific microarchitectural patterns. Furthermore, prototype implementation of the framework is described, followed by description of two experimental MLIP cores, rtl and pipe. These cores provide domain-specific languages for procedural generation of general-purpose RTL and pipelined hardware structures respectively. The developed means have been utilized for rapid designing of educational CPU core that has proved its operational capability in FPGA. We envision complementation of procedural hardware generation approach with microarchitecture-specific DSLs to be promising for raising the level of abstraction in microarchitecture design. This can reduce design duration of complex hardware units by up to two times, assuming either usage of common microarchitectural patterns or embodying of original ones in the new MLIP cores as an integral part of hardware design process.

Massive multi-core processing has recently attracted significant attention from the research community as one of the feasible solutions to satisfy constantly growing performance demands. However, this evolution path is nowadays hampered by the complexity and limited scalability of bus-oriented intra-chip communications infrastructure. The latest advantages of terahertz (THz) band wireless communications providing extraordinary capacity at the air interface offer a promising alternative to conventional wired solutions for intra-chip communications. Still, to invest resources in this field manufacturers need a clear vision of what are the performance and scalability gains of wireless intra-chip communications. Using the comprehensive hybrid methodology combining THz ray-tracing, direct CPU traffic measurements, and cycle-accurate CPU simulations, we perform the scalability study of x86 CPU design that is backward compatible with the current x86 architecture. We show that preserving the current cache coherence protocols mapped into the star wireless communications topology that allows for tight centralized medium access control a few hundreds of active cores can be efficiently supported without any notable changes in the x86 CPU logic. This important outcome allows for incremental development, where THz-assisted x86 CPU with a few dozens of cores can serve as an intermediate solution, while the truly massive multi-core system with broadcast-enabled medium access and enhanced cache coherence protocols can be an ultimate goal.