Raphael Behrle

Germanium (Ge) is recognized as a highly promising substrate for a broad spectrum of electronic, optical, and quantum applications, owing to its exceptional properties, including high charge carrier mobility, strong spin-orbit coupling, and its behavior as a quasi-direct semiconductor. However, the electron transfer effect in Ge, similar to the Gunn effect in GaAs, which induces negative differential resistance, has received relatively little attention thus far. This is likely due to the requirement for a well-defined material system and device architecture for its realization and usually at low temperatures.

Understanding the electronic transport of metal-semiconductor heterojunctions is of utmost importance for a wide range of emerging nanoelectronic devices like adaptive transistors, biosensors, and quantum devices. Here, we provide a comparison and in-depth discussion of the investigated Schottky heterojunction devices based on Si and Ge nanowires contacted with pure single-crystal Al. Key for the fabrication of these devices is the selective solid-state metal-semiconductor exchange of Si and Ge nanowires into Al, delivering void-free, single-crystal Al contacts with flat Schottky junctions, distinct from the bulk counterparts. Thereof, a systematic comparison of the temperature-dependent charge carrier injection and transport in Si and Ge by means of current-bias spectroscopy is visualized by 2D colormaps. Thus, it reveals important insights into the operation mechanisms and regimes that cannot be exploited by conventional single-sweep output and transfer characteristics. Importantly, it was found that the Al-Si system shows symmetric effective Schottky barrier (SB) heights for holes and electrons, whereas the Al-Ge system reveals a highly transparent contact for holes due to Fermi level pinning close to the valence band with charge carrier injection saturation due to a thinned effective SB. Moreover, thermionic field emission limits the overall electron conduction, indicating a distinct SB for electrons.

Ge-based bolometers are widely used for near-infrared detection for a broad range of applications such as thermography or chemical analysis. Notably, for the thermometers used in bolometers, integration, scaling, and sensitivity as well as functionality are of utmost importance. In this regard, Ge exhibits a favorable temperature sensitivity due to the relatively low bandgap and a high intrinsic charge carrier concentration. In this work, we demonstrate a nanoscale thermometer for bolometric applications on the base of Ge-on-insulator nanosheets with monolithic Al source/drain contacts envisioned for future wafer-scale integration. Importantly, electrostatic gating of the nanosheets allows the operation as a Schottky barrier field-effect transistor, providing tunability of the energy landscape and the involved charge carrier injection in interaction with the metal-semiconductor junctions. In this approach, the top-gate electrode and drain contact are connected, thus resembling a two-terminal device with bias-tunable temperature coefficient of resistance (TCR) values between 0%/K and −3.8%/K in the temperature range of T = 125–150 K. Moreover, in this configuration, even at room temperature, a maximum TCR value of −1.6%/K is achieved. The bias-tunable TCR exhibited in these devices may enable advanced concepts for room temperature bolometric applications and allow co-integration with nanoelectronics.

In this work, bottom‐up Al–Si–Al nanowire (NW) heterostructures are presented, which act as a prototype vehicle toward top‐down fabricated nanosheet (NS) and multi‐wire (MW) reconfigurable field‐effect transistors (RFETs). Evaluating the key parameters of these transistors regarding the on‐ and off‐currents as well as threshold voltages for n‐ and p‐type operation exhibit a high degree of symmetry. Most notably also a low device‐to‐device variability is achieved. In this respect, the investigated Al–Si material system reveals its relevance for reconfigurable logic cells obtained from Si NSs. To show the versatility of the proposed devices, this work reports on a combinational wired‐AND gate obtained from a multi‐gate RFET. Additionally, up‐scaling the current is achieved by realizing a MW RFET without compromising reconfigurability. The Al–Si–Al platform has substantial potential to enable complex adaptive and self‐learning combinational and sequential circuits with energy efficient and small footprint computing paradigms as well as for native components for hardware security circuits.

In this work, Al2O3-passivated, monolithic, and crystalline Al–Ge–Al heterostructure nanowire field effect transistors (FETs) with Ge channel lengths ranging from 18 to 826 nm are analyzed from a low-frequency noise perspective. 1/f and random telegraph noise (RTN) are analyzed in an accumulation mode, where the hole channel is formed by applying a back-gate potential VG. The normalized power spectral density of drain current fluctuations of 1/f noise (SID/ID2) at medium currents follows nearly an 1/ID trend. 1/f noise is analyzed within both the mobility and carrier number fluctuation models (MFM and CNFM), respectively. Taking the MFM into account, the Hooge noise parameter α spreads in the interval of 1.5 × 10−4 to 4 × 10−2, with lower values for shorter devices. Using the same data and the CNFM, the density of interface states Dit in the Al2O3/GexOy/Ge system was estimated using the transconductance extracted from the quasi-static transfer I/V characteristics. The extracted Dit values range from 5 × 109 to 3 × 1012 cm−2 eV−1. Contact noise has also been observed in some devices at high currents. RTN analyzed in time domain exhibits a relative RTN amplitude in the 0.3%–20% range. Capture and emission time constants as a function of VG exhibit a typical behavior for metal oxide semiconductor FETs. The extracted noise parameters are comparable with Ge and III–V nanodevices of top-down and bottom-up technologies.

Reconfigurable field‐effect transistors, capable of being dynamically programmed during run‐time, overcome the static nature of conventional complementary metal‐oxide semiconductors by reducing the transistor count and the circuit path delay. Thereby, SiGe and Ge are predicted to boost drive currents, switching speed and to reduce power consumption. Nevertheless, Ge‐based reconfigurable field‐effect transistor prototypes have so far fallen short in reaching both the promised performance due to interface instability to their contacts and gate oxides, as well as in reaching the current–voltage symmetry necessary for circuit applicability. Here, a top‐down fabricated SiGe‐based reconfigurable transistor technology is reported that is comprised of a vertical Si‐Si_0.67Ge_0.33 heterostructure enabling the envisioned high and symmetric on‐currents of both n‐ and p‐type operation. Monolithic integration with single‐elementary crystalline Al contacts alleviates process variability compared to conventional Ni‐silicide/Ni‐germanide contacts and introduces an ultra‐thin Si interlayer providing stability and equal injection efficiency of holes and electrons. The implementation of a three top‐gate transistor in combination with a hysteresis‐free Si/SiO₂/HfO₂ gate stack enhances polarity control and leakage current suppression to limit static power dissipation. Importantly, the obtained Al‐Si‐SiGe multi‐heterojunction and advanced reconfigurable transistor design is the first Ge‐based technology showing the envisioned stability and performance enhancements.

Si_1−xGe_x nanowires (NWs) were prepared by gold-supported chemical vapor deposition (CVD) using a single-source precursor with preformed Si–Ge bonds. Besides the tamed reactivity of the precursor, the approach reduces the process parameters associated with the control of decomposition characteristics and the dosing of individual precursors. The group IV alloy NWs are single crystalline with a constant diameter along their axis. During the wire growth by low pressure CVD, an Au-containing surface layer on the NWs forms by surface diffusion from the substrate, which can be removed by a combination of oxidation and etching. The electrical properties of the Si_1−xGe_x/Au core-shell NWs are compared to the Si_1−xGe_x NWs after Au removal. Core–shell NWs show signatures of metal-like behavior, while the purely semiconducting NWs reveal typical signatures of intrinsic Si_1−xGe_x. The synthesized materials should be of high interest for applications in nano- and quantum-electronics.

Si_1−xGe_xis a key material in modern complementary metal‐oxide‐semiconductor and bipolar devices. However, despite considerable efforts in metal‐silicide and ‐germanide compound material systems, reliability concerns have so far hindered the implementation of metal‐Si_1−xGe_xjunctions that are vital for diverse emerging “More than Moore” and quantum computing paradigms. In this respect, the systematic structural and electronic properties of Al‐Si_1−xGe_xheterostructures, obtained from a thermally induced exchange between ultra‐thin Si_1−xGe_xnanosheets and Al layers are reported. Remarkably, no intermetallic phases are found after the exchange process. Instead, abrupt, flat, and void‐free junctions of high structural quality can be obtained. Interestingly, ultra‐thin interfacial Si layers are formed between the metal and Si_1−xGe_xsegments, explaining the morphologic stability. Integrated into omega‐gated Schottky barrier transistors with the channel length being defined by the selective transformation of Si_1−xGe_xinto single‐elementary Al leads, a detailed analysis of the transport is conducted. In this respect, a report on a highly versatile platform with Si_1−xGe_xcomposition‐dependent properties ranging from highly transparent contacts to distinct Schottky barriers is provided. Most notably, the presented abrupt, robust, and reliable metal‐Si_1−xGe_xjunctions can open up new device implementations for different types of emerging nanoelectronic, optoelectronic, and quantum devices.

Overcoming the difficulty in the precise definition of the metal phase of metal-Si heterostructures is among the key prerequisites to enable reproducible next-generation nanoelectronic, optoelectronic, and quantum devices. Here, we report on the formation of monolithic Al-Si heterostructures obtained from both bottom-up and top-down fabricated Si nanostructures and AI contacts. This is enabled by a thermally induced Al-Si exchange reaction, which forms abrupt and void-free metal-semiconductor interfaces in contrast to their bulk counterparts. The selective and controllable transformation of Si NWs into Al provides a nanodevice fabrication platform with high-quality monolithic and single-crystalline Al contacts, revealing resistivities as low as rho = (6.31 +/- 1.17) x 10(-8) Omega m and breakdown current densities of J(max) = (1 +/- 0.13) X 10(12) Omega m(-2). Combining transmission electron microscopy and energy-dispersive X-ray spectroscopy confirmed the composition as well as the crystalline nature of the presented Al-Si-Al heterostructures, with no intermetallic phases formed during the exchange process in contrast to state-of-the-art metal silicides. The thereof formed single-element Al contacts explain the robustness and reproducibility of the junctions. Detailed and systematic electrical characterizations carried out on back- and top-gated heterostructure devices revealed symmetric effective Schottky barriers for electrons and holes. Most importantly, fulfilling compatibility with modern complementary metal-oxide semiconductor fabrication, the proposed thermally induced Al-Si exchange reaction may give rise to the development of nextgeneration reconfigurabIe electronics relying on reproducible nanojunctions.

Conventional field‐effect transistor (FET) concepts are limited to static electrical functions and demand extraordinarily steep and reproducible doping concentration gradients. Reaching the physical limits of scaling, doping‐free reconfigurable field‐effect transistors (RFETs) capable of dynamically altering the device operation between p‐ or n‐type, even during runtime, are emerging device concepts. In this respect, Ge has been identified as a promising channel material to enable reduction of power consumption and switching delay of RFETs. Nevertheless, its use has been limited to simulations and bottom‐up demonstrators not compatible with complex circuit technology. In this work, a deterministic top‐down fabrication scheme is demonstrated to realize a Ge‐based RFET architecture and exploring realizations with three independent gates. Polarity control and leakage current suppression are enabled by the specific injection of charge carriers through gated Al‐Ge heterojunctions and the introduction of a blocking electrostatic energy barrier. Further, the choice of monolithic Al/Ge contacts alleviates process variability compared to Ni‐germanide contacts presenting a top‐down technology platform for Ge‐based RFETs. Our device concept is a first step toward future integrated high‐performance and low‐power reconfigurable circuits, providing a platform for future energy‐efficient systems as well as hardware security integrated circuits.