Amir Bozorg

This article introduces a new discrete-time (DT) charge-sharing (CS) low-pass filter (LPF) that achieves high-order filtering and improves its stopband rejection while maintaining a reasonable duty cycle of the main clock at 20%. It proposes two key innovations: 1) a linear interpolation of the sampling capacitor and 2) a charge re-circulation of the history capacitors for deep stopband rejection. Fabricated in 28-nm CMOS, the proposed IIR LPF demonstrates a 1–9.9-MHz bandwidth (BW) programmability and achieves a record-high 120-dB stopband rejection at 100 MHz while consuming merely 0.92 mW. The in/out-of-band IIP3 is +17.7 dBm/+26.6 dBm, and the input-referred noise is 3.5 nV/ $\sqrt {\mathrm{ Hz}}$ .

In this article, we apply a new clock-phase reuse technique to a discrete-time infinite impulse response (IIR) complex-signaling bandpass filter (BPF). This leads to a deep improvement in filtering, especially the stopband rejection, while maintaining the area, sampling frequency, and the number of clock phases and their pulsewidths. Fabricated in 28-nm CMOS, the proposed BPF is highly tuneable and is capable of achieving a 70-dB stopband rejection at 50-MHz offset with 25% duty-cycle clocks while consuming 1.65 mW. The achieved in/out-of-band third-order intermodulation intercept point (IIP3) is +2.5 dB and +17.3 dBm, respectively, and the input-referred noise (IRN) is 1 ${\mathrm {nV}}/{\sqrt {\mathrm{ Hz}}}$ .

In this article, a new noise reduction/cancellation technique is proposed to improve noise figure (NF) of a broadband low-noise transconductance amplifier (LNTA) for 5G receivers. The LNTA combines a common-gate (CG) stage for wideband input matching and a common-source (CS) stage for canceling the noise and distortion of the CG stage. Yet, another noise reduction is applied to reduce the channel thermal noise of the noise cancellation stage itself. The technique further exploits current reuse and increases transconductance of the CS transistor while keeping its power consumption low. Fabricated in 28-nm CMOS, the proposed LNTA is capable of driving an external 50-Ω load and achieves a NF of 2.09-3.2 dB and input return loss (S₁₁) better than -10 dB over the 3-dB bandwidth of 20 MHz-4.5 GHz while consuming 4.5 mW from a single 1-V power supply. The achieved gain (S₂₁) and IIP3 are 15.2 dB and -4.6 dBm, respectively.