Vladimir Kolesnikov
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Previous Organizations / Institutes
The organizations / institutes from the scholar's other articles in the past ten years
Research Subjects
Research Interests
Vladimir Kolesnikov has a total of 47 co-authors. Here are the top co-authors by number of shared publications:
- David Heath
University of Illinois Urbana-Champaign, Urbana, Illinois, USA
7 shared publications - Carmit Hazay
Bar-Ilan University, Ramat Gan, Israel
6 shared publications - David Heath
Georgia Tech
6 shared publications - Yibin Yang
University of Toronto, Toronto, Canada
6 shared publications - Rafail Ostrovsky
UCLA
4 shared publications - Anasuya Acharya
Aarhus University
3 shared publications
Latest Publications
- Open Access
- 14 November 2026
- Published by Association for Computing Machinery (ACM)
- p. 645-659
ZEE200: Zero Knowledge for Everything and Everyone @ 200 KHz
- 14 November 2026
- Published by Association for Computing Machinery (ACM)
- p. 645-659
Open AccessZEE200: Zero Knowledge for Everything and Everyone @ 200 KHz
- Open Access
- 14 November 2026
- Published by Association for Computing Machinery (ACM)
- p. 6520-6534
Azkaban: A Zero-Knowledge Abstract Analysis for Neural Networks
- 14 November 2026
- Published by Association for Computing Machinery (ACM)
- p. 6520-6534
Open AccessAzkaban: A Zero-Knowledge Abstract Analysis for Neural Networks
- 12 August 2026
- Published by Springer Nature
- p. 397-429
Block-Accumulate Codes: Accelerated Linear Codes for PCGs and ZK
- 12 August 2026
- Published by Springer Nature
- p. 397-429
Block-Accumulate Codes: Accelerated Linear Codes for PCGs and ZK
- Open Access
- 8 December 2025
- Published by Springer Nature
- p. 35-67
Towards Building Efficient SCALES Protocols
- 8 December 2025
- Published by Springer Nature
- p. 35-67
Open AccessTowards Building Efficient SCALES Protocols
- Open Access
- 19 November 2025
- Published by Association for Computing Machinery (ACM)
- p. 4679-4691
Distance-Aware OT with Application to Fuzzy PSI
- 19 November 2025
- Published by Association for Computing Machinery (ACM)
- p. 4679-4691
Open AccessDistance-Aware OT with Application to Fuzzy PSI
- Open Access
- 19 November 2025
- Published by Association for Computing Machinery (ACM)
- p. 4634-4648
Toss: Garbled PIR from Table-Only Stacking
- 19 November 2025
- Published by Association for Computing Machinery (ACM)
- p. 4634-4648
Open AccessToss: Garbled PIR from Table-Only Stacking
- Open Access
- 17 August 2025
- Published by Springer Nature
- p. 556-588
Multiparty Garbling from OT with Linear Scaling and RAM Support
- 17 August 2025
- Published by Springer Nature
- p. 556-588
Open AccessMultiparty Garbling from OT with Linear Scaling and RAM Support
- 9 December 2024
- Published by Springer Nature
- p. 367-401
$\textsf{LogRobin}$++: Optimizing Proofs of Disjunctive Statements in VOLE-Based ZK- 9 December 2024
- Published by Springer Nature
- p. 367-401
$\textsf{LogRobin}$++: Optimizing Proofs of Disjunctive Statements in VOLE-Based ZK- Open Access
- 2 December 2024
- Published by Association for Computing Machinery (ACM)
- p. 3095-3109
Tight ZK CPU: Batched ZK Branching with Cost Proportional to Evaluated Instruction
We explore Zero-Knowledge Proofs (ZKPs) of statements expressed as programs written in high-level languages, e.g., C or assembly. At the core of executing such programs in ZK is the repeated evaluation of a CPU step, achieved by branching over the CPU's instruction set. This approach is general and covers traversal-execution of a program's control flow graph (CFG): here CPU instructions are straight-line program fragments (of various sizes) associated with the CFG nodes. This highlights the usefulness of ZK CPUs with a large number of instructions of varying sizes. We formalize and design an efficient tight ZK CPU, where the cost (both computation and communication, for each party) of each step depends only on the instruction taken. This qualitatively improves over state of the art, where cost scales with the size of the largest CPU instruction (largest CFG node). Our technique is formalized in the standard commit-and-prove paradigm, so our results are compatible with a variety of (interactive and non-interactive) general-purpose ZK. We implemented an interactive tight arithmetic (over F261-1) ZK CPU based on Vector Oblivious Linear Evaluation (VOLE) and compared it to the state-of-the-art non-tight VOLE-based ZK CPU Batchman (Yang et al. CCS'23). In our experiments, under the same hardware configuration, we achieve comparable performance when instructions are of the same size and a 5-18× improvement when instructions are of varied size. Our VOLE-based tight ZK CPU (over F261-1) can execute 100K (resp. 450K) multiplication gates per second in a WAN-like (resp. LAN-like) setting. It requires ≤ 102 Bytes per multiplication gate. Our basic building block, ZK Unbalanced Read-Only Memory, may be of independent interest.
- 2 December 2024
- Published by Association for Computing Machinery (ACM)
- p. 3095-3109
Open AccessTight ZK CPU: Batched ZK Branching with Cost Proportional to Evaluated Instruction
We explore Zero-Knowledge Proofs (ZKPs) of statements expressed as programs written in high-level languages, e.g., C or assembly. At the core of executing such programs in ZK is the repeated evaluation of a CPU step, achieved by branching over the CPU's instruction set. This approach is general and covers traversal-execution of a program's control flow graph (CFG): here CPU instructions are straight-line program fragments (of various sizes) associated with the CFG nodes. This highlights the usefulness of ZK CPUs with a large number of instructions of varying sizes. We formalize and design an efficient tight ZK CPU, where the cost (both computation and communication, for each party) of each step depends only on the instruction taken. This qualitatively improves over state of the art, where cost scales with the size of the largest CPU instruction (largest CFG node). Our technique is formalized in the standard commit-and-prove paradigm, so our results are compatible with a variety of (interactive and non-interactive) general-purpose ZK. We implemented an interactive tight arithmetic (over F261-1) ZK CPU based on Vector Oblivious Linear Evaluation (VOLE) and compared it to the state-of-the-art non-tight VOLE-based ZK CPU Batchman (Yang et al. CCS'23). In our experiments, under the same hardware configuration, we achieve comparable performance when instructions are of the same size and a 5-18× improvement when instructions are of varied size. Our VOLE-based tight ZK CPU (over F261-1) can execute 100K (resp. 450K) multiplication gates per second in a WAN-like (resp. LAN-like) setting. It requires ≤ 102 Bytes per multiplication gate. Our basic building block, ZK Unbalanced Read-Only Memory, may be of independent interest.