Tinghuan Chen

Approximate logic synthesis (ALS) is a promising design paradigm for error-resilient applications. It can automatically generate circuits with optimized delay, area, and power at the cost of small errors. Existing methods mainly apply local approximate changes (LACs) to shorten critical paths or reduce area. However, given the large search space of LACs, they struggle to achieve a good trade-off between both objectives. This restricts the timing optimization potential of approximate circuits, particularly since area savings can be reinvested to enhance the drive strength of timing-critical gates. This paper leverages population-based search to explore LACs with positive timing influence in parallel. We develop two LAC search actions specialized in critical path shortening and area reduction, respectively. Guided by a recommender system aware of circuit topology and quality, individuals iteratively execute suitable LAC search actions and refine their explored LAC sets by conflict-free combinations, thus balancing reductions in critical path depth and area. Area savings are then reinvested to enhance the drive strength of timing-critical gates, enabling further timing improvement. Experimental results show that compared to a state-of-the-art area-driven method, our framework further reduces 20.3% critical path delay with comparable area savings, while being 7.9× faster.

Artificial intelligence has achieved remarkable success in various real-world applications. However, the challenge lies in its implementation on hardware platforms with constrained resources and low power while maintaining real-time capabilities. Edge artificial intelligence, in particular, stands as a pivotal field for the practical deployment of AI. The 41st IEEE/ACM International Conference on Computer-Aided Design introduced the inaugural TinyML Design Contest in 2022. The contest entailed a rigorous, multi-month research and development competition, focusing on the creation of real-time detection algorithms for life-threatening ventricular arrhythmia. These algorithms were required to be deployable on the low-power microprocessor NUCLEO-L432KC. Open to multi-person teams worldwide, the contest garnered 150 teams participation teams from 50+ organizations, with 41 teams successfully completing the challenge. Our SEUer team secured the second place. This article provides a detailed exposition of the contest, offering insights into its structure and objectives. Furthermore, it analyzes and discusses the methods developed by some of the entries as well as representative results. Finally, the article concludes with directions for future improvements.

In logic synthesis, pre-optimization involves applying a sequence of transformations, referred to as a synthesis flow, to reduce the complexity of a circuit’s Boolean logic graph, such as the And-Inverter Graph (AIG). The primary challenge lies in selecting and ordering these transformations, a task complicated by the exponentially large solution space. In this work, we propose CB-EVO, a novel online learning framework that combines contextual bandit tuning with an evolutionary algorithm to efficiently explore the solution space and generate high-quality synthesis flows. The Syn-LinUCB algorithm functions as the pivotal agent in our bandit tuning process, incorporating circuit-specific characteristics and leveraging long-term payoffs to guide decision-making effectively, thereby circumventing the pitfalls of local optima. To complement the bandit algorithm, we design an evolutionary algorithm that accelerates the decision-making process and enables the efficient expansion of the sequence. Moreover, we explore practical heuristics, such as the “return-back” mechanism and the utilization of a choice network, to further enhance optimization outcomes. Experimental results demonstrate that our framework identifies the optimal synthesis flow with reduced computational time, significantly decreasing the number of AIG nodes and LUT count compared to state-of-the-art (SOTA) methods.

Analog circuit placement is crucial for optimal performance, but achieving a decent layout demands expertise and time. Recent advances in machine learning techniques have shown promising results in modeling analog layout performance. PAPlace further extends these methods and integrates them into the core analog placement engine, allowing direct optimization of the post-layout performance effectively. Our approach proposes a differentiable prediction model that combines layout and wiring information into a non-linear analog placement engine. We then incorporate the differentiable performance model into a gradient-descent-based global placement engine. A multi-objective optimization method is further proposed to find the common gradient descent direction for different metrics. The experimental results on benchmarks under the TSMC 40nm technology node demonstrate the superiority of the proposed framework compared with the cutting-edge works, with up to 2163.00μ V , 73.95dB, 62.25MHz, 57.84dB improvement in Offset Voltage, CMRR, BandWidth, DC Gain metrics.