Yu Cao

While the increasing resolution of Complementary Metal-Oxide-Semiconductor (CMOS) image sensors offers greater detail, it imposes significant computational burdens. Drawing inspiration from the human visual system, selective attention methods mitigate this by identifying and transmitting only the most informative pixels. However, pixel-wise selection often results in irregular regions that hinder downstream tasks and limit processing efficiency. To address these limitations, we propose the patch-wise selective transformer (PST). By shifting from pixel-level to patch-level processing, PST improves both selection accuracy and structural consistency. The framework incorporates a feature pyramid to capture multi-scale objects with richer feature representations. To further optimize efficiency, we introduce Selective Batchify Attention (SBA), which utilizes a lightweight gating layer to dynamically select and regroup informative tokens into new batches. This mechanism enables flexible token counts during Graphics Processing Unit (GPU) training and inference. Experimental results demonstrate that our approach achieves superior selection accuracy, minimizes information loss, and enhances object detection performance while significantly reducing computational overhead.

This paper presents ShiftMUX, a reconfigurable 4:1 multiplexer (MUX)-based in-memory computing (IMC) architecture for multiplier-less deep neural network (DNN) acceleration. The proposed design completes its operation in only three cycles, compared with at least ten cycles in prior approaches. Beyond basic logic, ShiftMUX supports complex functions such as full adder, full subtractor, and comparator, eliminating the need for separate mapping and control peripherals. When cascaded in a crossbar, multiple MUX units realize N-bit shift operations including logical, arithmetic, circular, and universal shifts enabling efficient power-of-two multiplications for quantized DNNs. Circuit-level simulations in 45nm technology show write energy of 32 pJ, read delay of 9.14 ps, and a total energy consumption of 240 pJ for a 4-bit multiplier, outperforming state-of-the-art designs. A Vision Transformer model exhibits only a +2.66% accuracy deviation with shift-based multiplication, confirming the suitability of ShiftMUX for modern AI models. Moreover, the architecture reduces computation overhead by more than 90%, requiring only N +log₂(N)+2 cycles, and achieves up to 9× speedup in multiplication. ShiftMUX thus provides a scalable, reconfigurable, and energy-efficient solution for low-latency DNN acceleration in edge and high-performance computing systems.

Monolithic designs face significant fabrication cost and data movement challenges, especially when executing complex and diverse AI models. Advanced 2.5D/3D packaging promises high bandwidth and connection density to overcome these challenges, yet it also introduces new electro-thermal constraints. This paper develops a suite of analytical performance models to enable efficient benchmarking of a 2.5D/3D heterogeneous system for energy-efficient AI computing. These models encompass various performance metrics related to computing units, network-on-chip, and network-on-package. The results are summarized into a new tool, HISIM, which is 104–106× faster than state-of-the-art AI benchmark tools. Furthermore, HISIM integrates rapid thermal simulation for the 2.5D/3D system, helping shed light on both the potential and limitations of 2.5D/3D heterogeneous integration on representative AI algorithms. The code of HISIM is available at https://github.com/mec-UMN/HISIM.

In recent years, the long-range attention mechanism of vision transformers has driven significant performance breakthroughs across various computer vision tasks. However, the traditional self-attention mechanism, which processes both informative and non-informative tokens, suffers from inefficiency and inaccuracies. While sparse attention mechanisms have been introduced to mitigate these issues by pruning tokens involved in attention, they often lack context-awareness and intelligence. These mechanisms frequently apply a uniform token selection strategy across different inputs for batch training or optimize efficiency only for the inference stage. To overcome these challenges, we propose a novel algorithm: Select and Pack Attention (SPA). SPA dynamically selects informative tokens using a low-cost gating layer supervised by selection labels and packs these tokens into new batches, enabling a variable number of tokens to be used in parallelized GPU batch training and inference. Extensive experiments across diverse datasets and computer vision tasks demonstrate that SPA delivers superior performance and efficiency, including a 0.6 mAP improvement in object detection and a 16.4% reduction in computational costs.

Cryogenic CMOS is a promising technology for high performance computing due to its improvement in subthreshold slope, carrier mobilities and reduced wire resistance. The threshold voltage (V_th) increase at 77K can be mitigated by metal gate work function (PHIG) engineering to achieve matched off current (I_off) further enhancing the device performance allowing us to operate at very low supply voltage thereby reducing the Energy Delay Product (EDP). However, the effect of variation on noise margins of static random access memories (SRAM) deploying these matched I_off devices is very prominent especially at low supply voltages (V_dd) limiting its scaling. In this work, we propose a framework to perform V_th retargeting for cryogenic SRAM for improving noise margins in high performance cryogenic SRAM cells under variation. The proposed framework comprises of a Monte-Carlo engine which performs statistical analysis and DC characterization and a backend processing engine to analyze noise margins and tune the PHIG. To demonstrate the framework, we use calibrated 14nm FinFET models at 300K and 77K. First, we analyze the logic blocks using iso-I_off devices, which yield up to 3x improvement in delay at iso-energy and a 4.5x reduction in energy at iso-delay. Next, we study the effect of V_th variation on the device currents. Finally, the framework is deployed to tune PHIG, and results show that it can enhance the noise margins by 23%, 31% and 19% for hold, read and write operations respectively at 77K compared to iso-I_off devices. Further, a 1kb SRAM array has been simulated using iso-I_off tuned peripherals and framework tuned SRAM cells, and it shows 5.4x reduction in read/write energies along with 1.2x delay reduction and better noise margins at 77K compared to 300K.