Mahadeva Iyer Natarajan
Mahadeva Iyer Natarajan has a total of 19 co-authors. Here are the top co-authors by number of shared publications:
- Steven Thijs
Department of Electrical Engineering (ESAT) of KU Leuven, Leuven, Belgium
3 shared publications D. Linten
Hanwa Electronic Industries, Ogata, Wakayama, Japan
2 shared publications- David Tremouilles
LAAS, (31400 TOULOUSE)
2 shared publications - Guido Groeseneken
ESAT Department, Katholieke Universiteit Leuven, Leuven, Belgium
2 shared publications S. Decoutere
IMEC, Leuven, Belgium
2 shared publications- Wutthinan Jeamsaksiri
Thai Microelectronics Center, National Electronics and Computer Technology Center, Chachoengsao 24000, Thailand
2 shared publications
Latest Publications
- 21 May 2018
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 39 (7) , 1011-1013
Engineering ESD Robust LDMOS SCR Devices in FinFET Technology
A robust FinFET silicon-controlled rectifier (SCR) LDMOS ESD protection device is developed. Replacing the drain contact implant to the P+ implant from N+ implant creates an SCR inside the LDMOS and when the N+ contact is removed a Schottky SCR LDMOS is created. The ESD performance of the baseline FinFET LDMOS is Zero, while that of the SCR LDMOS is 9.2mA/um and Schottky SCR is 4.6mA/um respectively.
- 21 May 2018
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 39 (7) , 1011-1013
Engineering ESD Robust LDMOS SCR Devices in FinFET Technology
A robust FinFET silicon-controlled rectifier (SCR) LDMOS ESD protection device is developed. Replacing the drain contact implant to the P+ implant from N+ implant creates an SCR inside the LDMOS and when the N+ contact is removed a Schottky SCR LDMOS is created. The ESD performance of the baseline FinFET LDMOS is Zero, while that of the SCR LDMOS is 9.2mA/um and Schottky SCR is 4.6mA/um respectively.
- 5 January 2007
- Published by Elsevier in Microelectronics Reliability
- Vol. 47 (7) , 1016-1024
Transient voltage overshoot in TLP testing – Real or artifact?
- 5 January 2007
- Published by Elsevier in Microelectronics Reliability
- Vol. 47 (7) , 1016-1024
Transient voltage overshoot in TLP testing – Real or artifact?
- 27 July 2005
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 19461542,p. 59-66
RFCMOS ESD protection and reliability
This paper addresses the ESD reliability issues in RFICs, focusing on the technology impact on the device and design. We also present the basic RF ESD protection methods used in industry. Presents the general topology of a 5 GHz LNA, which is protected using several ESD protection methodologies, and describes the 90 nm CMOS process technology used for the fabrication of the LNA. The measurement procedures used for the evaluation of stand-alone devices and LNAs are described. The ESD performance of standard ESD protection devices is reviewed and presents results and discussions on the ESD reliability of various ESD protection methods employed from the device point of view, followed by an outlook on the future RF ESD challenges, and conclusions.
- 27 July 2005
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 19461542,p. 59-66
RFCMOS ESD protection and reliability
This paper addresses the ESD reliability issues in RFICs, focusing on the technology impact on the device and design. We also present the basic RF ESD protection methods used in industry. Presents the general topology of a 5 GHz LNA, which is protected using several ESD protection methodologies, and describes the 90 nm CMOS process technology used for the fabrication of the LNA. The measurement procedures used for the evaluation of stand-alone devices and LNAs are described. The ESD performance of standard ESD protection devices is reviewed and presents results and discussions on the ESD reliability of various ESD protection methods employed from the device point of view, followed by an outlook on the future RF ESD challenges, and conclusions.
- 22 November 2004
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 291-294
A 5 GHz fully integrated ESD-protected low-noise amplifier in 90 nm RF CMOS
A 5.5 GHz fully integrated low-power ESD-protected low-noise amplifier (LNA), designed and verified in a 90 nm RF CMOS technology, is presented for the first time. This 9.7 mW LNA features a 13.3 dB power gain with a noise figure of 2.9 dB, while maintaining an input return loss of -14 dB.
- 22 November 2004
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 291-294
A 5 GHz fully integrated ESD-protected low-noise amplifier in 90 nm RF CMOS
A 5.5 GHz fully integrated low-power ESD-protected low-noise amplifier (LNA), designed and verified in a 90 nm RF CMOS technology, is presented for the first time. This 9.7 mW LNA features a 13.3 dB power gain with a noise figure of 2.9 dB, while maintaining an input return loss of -14 dB.