Shawn D. Burnham
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Research Subjects
Shawn D. Burnham has a total of 29 co-authors. Here are the top co-authors by number of shared publications:
- Miroslav Micovic
HRL Laboratories, LLC, Malibu, CA, USA
4 shared publications Ming Hu
HRL Laboratories, LLC., 3011 Malibu Canyon Rd., Malibu, California, 90265, USA
2 shared publicationsPaul Hashimoto
HRL Laboratories, LLC., 3011 Malibu Canyon Rd., Malibu, California, 90265, USA
2 shared publicationsRoss Bowen
HRL Laboratories, LLC at 3011 Malibu Canyon Rd., Malibu, California, 90265, USA, 310-317-5000
2 shared publicationsA. Kurdoghlian
HRL Laboratories, LLC, Malibu, CA, USA
1 shared publicationB. Grabar
HRL Laboratories, LLC, Malibu, CA, USA
1 shared publication
Latest Publications
- 17 October 2017
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 38 (12) , 1708-1711
GaN DHFETs Having 48% Power Added Efficiency and 57% Drain Efficiency at $V$ -BandWe report the state-of-the-art$V$ -band power performance of a scaled 40-nm gate length Al0.23Ga0.77N/AlN/GaN/Al0.08Ga0.92N double heterojunction field effect transistor (DHFET). The$200~\mu \text{m}$ ($4\times 50 ~\mu \text{m}$ ) wide GaN DHFETs pre-matched for$V$ -band (57–64 GHz) have demonstrated an output power of 376 mW (1.88 W/mm) with 48% power-added efficiency (PAE), 57% drain efficiency, and more than 8 dB of associated gain measured at a frequency of 59 GHz. These results represent to the best of our knowledge the best combination of power and PAE reported to date at this frequency for a solid-state device. These results were achieved through optimization of the GaN heterostructure, which incorporates a low aluminum content back-barrier for electron confinement through polarization effects, a vertically scaled Al0.23Ga0.77N/AlN gate barrier stack for minimization of short-channel effects, and a selective n+ GaN ohmic re-growth process by molecular beam epitaxy for reduction of parasitic resistance.- 17 October 2017
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 38 (12) , 1708-1711
GaN DHFETs Having 48% Power Added Efficiency and 57% Drain Efficiency at $V$ -BandWe report the state-of-the-art$V$ -band power performance of a scaled 40-nm gate length Al0.23Ga0.77N/AlN/GaN/Al0.08Ga0.92N double heterojunction field effect transistor (DHFET). The$200~\mu \text{m}$ ($4\times 50 ~\mu \text{m}$ ) wide GaN DHFETs pre-matched for$V$ -band (57–64 GHz) have demonstrated an output power of 376 mW (1.88 W/mm) with 48% power-added efficiency (PAE), 57% drain efficiency, and more than 8 dB of associated gain measured at a frequency of 59 GHz. These results represent to the best of our knowledge the best combination of power and PAE reported to date at this frequency for a solid-state device. These results were achieved through optimization of the GaN heterostructure, which incorporates a low aluminum content back-barrier for electron confinement through polarization effects, a vertically scaled Al0.23Ga0.77N/AlN gate barrier stack for minimization of short-channel effects, and a selective n+ GaN ohmic re-growth process by molecular beam epitaxy for reduction of parasitic resistance.- 4 September 2017
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Semiconductor Manufacturing
- Vol. 30 (4) , 480-485
Reliability Characteristics and Mechanisms of HRL’s T3 GaN Technology
HRL’s T3 GaN MMIC technology is evaluated using DC reliability experiments, including a voltage step-stress test, a temperature step-stress test, and a 3-temperature life test. The drain voltage step-stress test revealed three distinct regions of operation through gate leakage characteristic changes: burn-in stabilization up to 5 V, followed by stable operation up to 20 V, then voltage-dependent degradation up to catastrophic failure around 30 V. As a result, a de-rated recommended safe-operating limit of Vds = 12V was established. The temperature step-stress test resulted in clear Arrhenius temperature-dependent degradation of the device on-resistance above 250 °C. Similarly, a recommended safe-operating limit of 150 °C was established for the technology. Finally, the 3-temperature life test resulted in clear temperature group separation and an activation energy of 2.52 eV, with a mean time-to-failure of 4 million hours at 150 °C with only a +0.2 ohm.mm increase in device on-resistance. Physical failure analysis of degraded parts showed the mechanism was a defect formation in the epitaxial barrier layer at the drain edge of the gate. Finite-element electrical simulations duplicated this degradation mechanism by modeling the defect as a void, which depleted the 2DEG and therefore increased device on-resistance.
- 4 September 2017
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Semiconductor Manufacturing
- Vol. 30 (4) , 480-485
Reliability Characteristics and Mechanisms of HRL’s T3 GaN Technology
HRL’s T3 GaN MMIC technology is evaluated using DC reliability experiments, including a voltage step-stress test, a temperature step-stress test, and a 3-temperature life test. The drain voltage step-stress test revealed three distinct regions of operation through gate leakage characteristic changes: burn-in stabilization up to 5 V, followed by stable operation up to 20 V, then voltage-dependent degradation up to catastrophic failure around 30 V. As a result, a de-rated recommended safe-operating limit of Vds = 12V was established. The temperature step-stress test resulted in clear Arrhenius temperature-dependent degradation of the device on-resistance above 250 °C. Similarly, a recommended safe-operating limit of 150 °C was established for the technology. Finally, the 3-temperature life test resulted in clear temperature group separation and an activation energy of 2.52 eV, with a mean time-to-failure of 4 million hours at 150 °C with only a +0.2 ohm.mm increase in device on-resistance. Physical failure analysis of degraded parts showed the mechanism was a defect formation in the epitaxial barrier layer at the drain edge of the gate. Finite-element electrical simulations duplicated this degradation mechanism by modeling the defect as a void, which depleted the 2DEG and therefore increased device on-resistance.
- 20 June 2011
- Published by Wiley in physica status solidi (c)
- Vol. 8 (7-8) , 2399-2403
Reliability of T‐gate AlGaN/GaN HEMTs
- 20 June 2011
- Published by Wiley in physica status solidi (c)
- Vol. 8 (7-8) , 2399-2403
Reliability of T‐gate AlGaN/GaN HEMTs
- 20 July 2010
- Published by Wiley in physica status solidi (c)
- Vol. 7 (7-8) , 2010-2012
Gate‐recessed normally‐off GaN‐on‐ Si HEMT using a new O2‐BCl3 digital etching technique
A new, semi‐self‐limiting, digital etch process using separate oxygen (O2) and boron trichloride (BCl3) plasmas to sequentially remove layers of material from AlGaN/GaN high electron mobility transistors (HEMTs) on the order of a few angstroms per cycle is presented. This novel digital or atomic layer etching (ALE) technique was used for the conversion of AlGaN/GaN HEMT devices from depletion mode (normally‐on operation) to enhancement mode (normally‐off operation). For a fixed BCl3 time of 60 sec per cycle, the etch rate per cycle was increased from 1.4 nm/cycle to 2.5 nm/cycle by increasing the O2 time per cycle from zero to 15 seconds, and remained fairly constant with higher O2 time per cycle for a self‐limiting etch process. Two GaN‐on‐Si wafers from the same CVD growth were processed side‐by‐side using the device layout and process steps, except for the depletion‐to‐enhancement conversion step, to compare ALE and fluorine treatment. The ALE‐processed had a peak gm of 250 mS/mm, 67% higher than the fluorine‐treatment process. The ALE process resulted in a threshold voltage variation of +/‐ 150 mV across the 3 inch wafer (σ = 63 mV), which was less than half of that of the fluorine‐treatment wafer. The three‐terminal breakdown voltage of the ALE‐processed wafer exceeded 1100 V, which is the first demonstration of such a high voltage device using GaN‐on‐Si and a gate recess technique, and the drain leakage current was in the μA/mm range at 1100 V.
- 20 July 2010
- Published by Wiley in physica status solidi (c)
- Vol. 7 (7-8) , 2010-2012
Gate‐recessed normally‐off GaN‐on‐ Si HEMT using a new O2‐BCl3 digital etching technique
A new, semi‐self‐limiting, digital etch process using separate oxygen (O2) and boron trichloride (BCl3) plasmas to sequentially remove layers of material from AlGaN/GaN high electron mobility transistors (HEMTs) on the order of a few angstroms per cycle is presented. This novel digital or atomic layer etching (ALE) technique was used for the conversion of AlGaN/GaN HEMT devices from depletion mode (normally‐on operation) to enhancement mode (normally‐off operation). For a fixed BCl3 time of 60 sec per cycle, the etch rate per cycle was increased from 1.4 nm/cycle to 2.5 nm/cycle by increasing the O2 time per cycle from zero to 15 seconds, and remained fairly constant with higher O2 time per cycle for a self‐limiting etch process. Two GaN‐on‐Si wafers from the same CVD growth were processed side‐by‐side using the device layout and process steps, except for the depletion‐to‐enhancement conversion step, to compare ALE and fluorine treatment. The ALE‐processed had a peak gm of 250 mS/mm, 67% higher than the fluorine‐treatment process. The ALE process resulted in a threshold voltage variation of +/‐ 150 mV across the 3 inch wafer (σ = 63 mV), which was less than half of that of the fluorine‐treatment wafer. The three‐terminal breakdown voltage of the ALE‐processed wafer exceeded 1100 V, which is the first demonstration of such a high voltage device using GaN‐on‐Si and a gate recess technique, and the drain leakage current was in the μA/mm range at 1100 V.