Minghua Tang

This work presents a high-stability self-rectifying memristor (SRM) array based on the Pt/TaO_x/Ti structure, with an in-depth investigation of the performance and potential applications of the device. The device demonstrates excellent rectification and on/off ratios, along with low-power readout, multi-state storage, and multi-level switching capabilities, highlighting its practicality and adaptability. Notably, the device exhibits outstanding fluctuation suppression and exceptional uniformity. The coefficient of variation (CV) of the rectification ratio, calculated as 0.11497 at 3 V, indicates its high stability under multiple cycles and low-voltage operation, making it well-suited for large-scale integration and operational applications. Moreover, the stability of the rectification ratio further reinforces its potential as a hardware foundation for large-scale in-memory computing systems. By combining the neuromorphic characteristics of the device with a simulated annealing algorithm and optimizing the annealing temperature function, the system emulates biological neuron behavior, enabling fast and efficient image restoration tasks. Experimental results demonstrate that this approach significantly outperforms traditional algorithms in both optimization speed and repair accuracy. The present study offers a novel perspective for the design of in-memory computing hardware and showcases promising applications in neuromorphic computing and image processing.

Despite the tremendous potential of in-memory computing (IMC) for AI applications, analog IMC still faces critical challenges related to noise sensitivity and computational accuracy, largely due to intrinsic non-idealities. These limitations significantly restrict the scalability and real-world deployability of analog IMC systems. To address accuracy degradation caused by hardware noise, we propose a comprehensive framework integrating noise modeling, noise-aware training (NAT), and hardware-adaptive compensation (HAC). Specifically, a noise model is derived from empirical measurements of a 40nm eFlash-based IMC SoC to capture diverse noise sources. The NAT scheme embeds the noise model into the training pipeline to enhance algorithm robustness, while the noise model guides HAC to mitigate the effects of device- and circuit-level variations during inference. Experimental results demonstrate that the noise model achieves a cosine similarity above 0.99 with actual chip behavior. In a speech denoising task, NAT improves the perceptual evaluation of speech quality (PESQ) by 0.168 (6.82%), while HAC reduces the output error variance by an average of 74.68%. Applied to multiple tasks including speech wake-up, speech denoising and image super-resolution, our framework achieves improvements of 13.5% in wake-up accuracy, 0.7 (29.2%) in PESQ, and 2.82 dB (7.2%) in peak signal-to-noise ratio (PSNR), respectively. These results demonstrate the generality and effectiveness of the proposed framework across a range of AI tasks.

The negative capacitance (NC) effect in ferroelectric (FE) materials offers promising potential for low-power electronics and energy storage. This study investigates the strain-engineered NC behaviour of PbZr_0.5Ti_0.5O₃ (PZT) thin films using Landau-Khalatnikov theory coupled with mechanical boundary conditions. Unlike conventional models that assume a constant Curie temperature, our framework incorporates strain-dependent ferroelectric transition temperatures, which is more accurate for strain tuning of NC. Static and dynamic simulations reveal that compressive and tensile strains significantly enhance the NC effect by amplifying energy barriers, negative curvature in free energy profiles, and transient voltage drop magnitudes. Compressive strains can exhibit superior performance, increasing polarization-electric field (P-E) hysteresis slopes and transient NC responses. While tensile strains show non-classical NC enhancement, which is different from the reported results. The model predicts prolonged voltage drop durations (Δ t ≈ 6.5 μs) and amplitudes (ΔV ≈ 1.5 V) under compressive strain (ε = −0.4%), aligning with experimental results. The NC Field-Effect Transistors (NC-FETs) under compressive strain demonstrate a 4.7 × enhancement in current while simultaneously achieving a sub-thermal limit subthreshold swing (SS) of 22.6 mV dec⁻¹ at V _gs = 0.57 V, surpassing the tensile strain efficacy. The improved model exhibits current elevation and SS reduction compared to the traditional model predictions. These results highlight the necessity of intrinsic strain characterization during fabrication and validate strain-polarity asymmetry in NC modulation. The work reveals the significance of addressing the strain-dependent FE phase transition temperature, offering a robust framework for optimizing strain-engineered NC devices.

In-memory computing (IMC) has emerged as a promising approach for accelerating deep neural network (DNN) inference by relocating computations to memory arrays. However, the efficacy of analog IMC diminishes when higher computational precision is required due to inherent device non-idealities. In this paper, we present a reconfigurable heterogeneous architecture that integrates a digital computing unit (DCU) with an analog IMC unit (AIMCU). The computational data is partitioned into most significant bits (MSBs) and least significant bits (LSBs); the sparse MSBs are processed by the DCU with lossless precision, and the dense LSBs are computed by the AIMCU for high energy efficiency, thereby enhancing inference accuracy and optimizing area efficiency. The architecture also features multiple modes that support variable-precision input splitting and weight splitting computation. Additionally, by leveraging hardware characteristics, we have developed several optimization strategies for neural network deployment, including parameter splitting, shifting algorithms, and sparse weight mapping. The experimental results show that the perceptual evaluation of speech quality (PESQ) of the deep complex convolution recurrent network (DCCRN) improved by 28.98%, while the peak signal-to-noise ratio (PSNR) of the super-resolution network (SRN) increased by 17.27%. Compared to previous state-of-the-art (SOTA) work, the reconfigurable heterogeneous-IMC-based system on a chip (SoC) demonstrates a significant improvement in energy efficiency while achieving accuracy close to that of pure digital computing.

Oxide‐based self‐rectifying memristors have emerged as promising candidates for the construction of neural networks, owing to their advantageous features such as high‐density integration, low power consumption, 3D stackability, straightforward fabrication processes, and compatibility with complementary metal‐oxide‐semiconductor (CMOS) technology. Notwithstanding these merits, there remains considerable scope for the suppression of parasitic currents in large‐scale memristor arrays, which poses a notable challenge in the development of extensive neural networks capable of executing intricate computational tasks. This study introduces a 1 kbit self‐rectifying memristor array based on Pt/HfO ₂ /Ti structural units. Individual devices in this array not only exhibit switching ratios exceeding 10 ³ , but also maintain rectification ratios greater than 10 ⁵ , and their excellent negative rectification performance effectively suppresses latent path currents in the array. Moreover, the convolutional calculation logic and forward inference process of 8‐bit neural networks are demonstrated based on this array, which verifies the feasibility of using arrays to simulate convolutional neural networks for all hardware operations. Ultimately, a complete convolutional neural network system is constructed, the system achieving a recognition rate of up to 98% in the handwriting recognition task. This work provides a new strategy toward the implementation of all‐hardware computing for convolutional neural networks.

Iterative linear solvers are a crucial kernel in many numerical analysis problems. The performance and energy efficiency of iterative solvers based on traditional architectures are severely constrained by the memory wall bottleneck. Computing-in-memory (CIM) has the potential to enhance solving efficiency. Existing CIM architectures are mostly customized for specific algorithms and primarily focus on handling fixed-point operations, which makes them difficult to meet the demands of diverse and high-precision applications. In this work, we propose a CIM architecture that natively supports various iterative linear solvers based on floating-point operations. We develop a new instruction set for the accelerator, which can be flexibly combined to implement various iterative solvers. The evaluation results show that, compared with the GPU implementation, our accelerator achieves more than 10.1× speedup and 6.8× energy savings when executing different iterative solvers.

Based on the simulation software, single-event transient (SET) simulations were conducted on semi-enclosed gate NMOS devices. The simulation involved bombarding the semi-enclosed gate NMOS devices with heavy ions under specific conditions. A comparative analysis was conducted to evaluate the single-event transient tolerance of traditional NMOS and semi-enclosed gate NMOS. Simulation curves from transient to steady-state states under different Linear Energy Transfer (LET) values, as well as potential distribution and current density distribution maps following heavy ion bombardment, were analyzed. Furthermore, single-event transient simulations were carried out on inverters composed of both NMOS types, with subsequent analysis. The results ultimately demonstrate that the semi-enclosed gate NMOS exhibits superior single-event transient tolerance compared to conventional NMOS.