Federico Fary
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Research Subjects
Federico Fary has a total of 4 co-authors. Here are the top co-authors by number of shared publications:
- Andreas Baschirotto
Department of Physics “G. Occhialini”, University of Milano-Bicocca, 20126 Milano, Italy
3 shared publications - Elia Arturo Vallicelli
Department of Physics, University of Milano-Bicocca, 20126 Milano, Italy
2 shared publications - Marcello De Matteis
Department of Physics, University of Milano Bicocca, Piazza della Scienza 3, 20126 Milano, Italy
2 shared publications - Nicolas Galante
Politecnico di Torino, Torino, Italy
1 shared publication
Latest Publications
- 9 July 2021
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems II: Express Briefs
- Vol. 68 (9) , 3068-3072
64 dB Dynamic-Range 810 μW 90 MHz Fully-Differential Flipped-Source-Follower Analog Filter in 28nm-CMOS
This brief presents a 4 th -order continuous-time analog filter based on Flipped-Source-Follower stage. Source-Follower (SF) filters typically adopt pseudo-differential topology (critical for matching and bulk/substrate noise rejection) and are realized in not recent CMOS processes (130nm or 180nm) due to the intrinsic voltage headroom required by SF operation. The proposed device solves the above limitations by proposing a fully-differential circuital topology, which improves by 13 dB the power supply rejection with respect to pseudo differential approach, and by operating in 28nm-CMOS process, thanks to a proper level-shifter transistor, which enables optimum biasing point and enhances filter dynamic range. The prototype is composed by the cascade of two biquadratic cells. It features 90 MHz -3 dB bandwidth, and consumes 816 μW power (408 μW per cell) from a 1V supply. Dynamic-Range is 64 dB with 140 μV RMS output noise, and at 0.32 V 0-PEAK differential output voltage swing. Figure-of-Merit is 156 dBJ $^{-1}$ .- 9 July 2021
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems II: Express Briefs
- Vol. 68 (9) , 3068-3072
64 dB Dynamic-Range 810 μW 90 MHz Fully-Differential Flipped-Source-Follower Analog Filter in 28nm-CMOS
This brief presents a 4 th -order continuous-time analog filter based on Flipped-Source-Follower stage. Source-Follower (SF) filters typically adopt pseudo-differential topology (critical for matching and bulk/substrate noise rejection) and are realized in not recent CMOS processes (130nm or 180nm) due to the intrinsic voltage headroom required by SF operation. The proposed device solves the above limitations by proposing a fully-differential circuital topology, which improves by 13 dB the power supply rejection with respect to pseudo differential approach, and by operating in 28nm-CMOS process, thanks to a proper level-shifter transistor, which enables optimum biasing point and enhances filter dynamic range. The prototype is composed by the cascade of two biquadratic cells. It features 90 MHz -3 dB bandwidth, and consumes 816 μW power (408 μW per cell) from a 1V supply. Dynamic-Range is 64 dB with 140 μV RMS output noise, and at 0.32 V 0-PEAK differential output voltage swing. Figure-of-Merit is 156 dBJ $^{-1}$ .- Open Access
- 30 March 2021
- Published by MDPI AG in Journal of Low Power Electronics and Applications
- Vol. 11 (2) , 15
A 28 nm CMOS 100 MHz 67 dB-Dynamic-Range 968 µW Flipped-Source-Follower Analog Filter
This paper presents a fourth-order continuous-time analog filter based on the cascade of two flipped-source-follower (FSF) biquadratic (biquad) cells. The FSF biquad adopts two interacting loops (the first due to the classic source-follower, and the second to the additional gain path) which lower the impedances of all circuit nodes with relevant benefits in terms of noise power reduction and linearity enhancement. The presented device was integrated in 28 nm CMOS and featured 100 MHz −3 dB bandwidth with 67 dB Dynamic-Range. Input IP3 was 12 dBm at 10 and 11 MHz input tone frequencies. Total power consumption was 0.968 mW (0.484 mW per cell). Hence, the filter performed one of the highest figures-of-merit (160.7 dBJ-1) compared with analog state-of-the-art filters.
- 30 March 2021
- Published by MDPI AG in Journal of Low Power Electronics and Applications
- Vol. 11 (2) , 15
Open AccessA 28 nm CMOS 100 MHz 67 dB-Dynamic-Range 968 µW Flipped-Source-Follower Analog Filter
This paper presents a fourth-order continuous-time analog filter based on the cascade of two flipped-source-follower (FSF) biquadratic (biquad) cells. The FSF biquad adopts two interacting loops (the first due to the classic source-follower, and the second to the additional gain path) which lower the impedances of all circuit nodes with relevant benefits in terms of noise power reduction and linearity enhancement. The presented device was integrated in 28 nm CMOS and featured 100 MHz −3 dB bandwidth with 67 dB Dynamic-Range. Input IP3 was 12 dBm at 10 and 11 MHz input tone frequencies. Total power consumption was 0.968 mW (0.484 mW per cell). Hence, the filter performed one of the highest figures-of-merit (160.7 dBJ-1) compared with analog state-of-the-art filters.
- Open Access
- 28 October 2020
- Published by MDPI AG in Journal of Low Power Electronics and Applications
- Vol. 10 (4) , 35
A 100 MHz 0.41 fJ/(Bit∙Search) 28 nm CMOS-Bulk Content Addressable Memory for HEP Experiments
This paper presents a transistor-level design with extensive experimental validation of a Content Addressable Memory (CAM), based on an eXclusive OR (XOR) single-bit cell. This design exploits a dedicated architecture and a fully custom approach (both in the schematic and the layout phase), in order to achieve very low-power and high-speed performances. The proposed architecture does not require an internal clock or pre-charge phase, which usually increase the power request and slow down data searches. On the other hand, the dedicated solutions are exploited in order to minimize parasitic layout-induced capacitances in the single-bit cell, further reducing the power consumption. The prototype device, named CAM-28CB, is integrated in the deeply downscaled 28 nm Complementary Metal-Oxide-Semiconductor (CMOS) Bulk (28CB) technology. In this way, the high transistor transition frequency and the intrinsic lower parasitic capacitances allow the system speed to be improved. Furthermore, the high radiation hardness of this technology node (up to 1Grad TID), together with the CAM-28CB high-speed and low-power performances, makes this device suitable for High-Energy Physics experiments, such as ATLAS (A Toroidal LHC ApparatuS) at Large Hadron Collider (LHC). The prototype operates at a frequency of up to 100 MHz and consumes 46.86 µW. The total area occupancy is 1702 µm2 for 1.152 kb memory bit cells. The device operates with a single supply voltage of 1 V and achieves 0.41 fJ/bit/search Figure-of-Merit.
- 28 October 2020
- Published by MDPI AG in Journal of Low Power Electronics and Applications
- Vol. 10 (4) , 35
Open AccessA 100 MHz 0.41 fJ/(Bit∙Search) 28 nm CMOS-Bulk Content Addressable Memory for HEP Experiments
This paper presents a transistor-level design with extensive experimental validation of a Content Addressable Memory (CAM), based on an eXclusive OR (XOR) single-bit cell. This design exploits a dedicated architecture and a fully custom approach (both in the schematic and the layout phase), in order to achieve very low-power and high-speed performances. The proposed architecture does not require an internal clock or pre-charge phase, which usually increase the power request and slow down data searches. On the other hand, the dedicated solutions are exploited in order to minimize parasitic layout-induced capacitances in the single-bit cell, further reducing the power consumption. The prototype device, named CAM-28CB, is integrated in the deeply downscaled 28 nm Complementary Metal-Oxide-Semiconductor (CMOS) Bulk (28CB) technology. In this way, the high transistor transition frequency and the intrinsic lower parasitic capacitances allow the system speed to be improved. Furthermore, the high radiation hardness of this technology node (up to 1Grad TID), together with the CAM-28CB high-speed and low-power performances, makes this device suitable for High-Energy Physics experiments, such as ATLAS (A Toroidal LHC ApparatuS) at Large Hadron Collider (LHC). The prototype operates at a frequency of up to 100 MHz and consumes 46.86 µW. The total area occupancy is 1702 µm2 for 1.152 kb memory bit cells. The device operates with a single supply voltage of 1 V and achieves 0.41 fJ/bit/search Figure-of-Merit.