Wenqi Wu

Join is an important but data-intensive and compute-intensive operation in database systems. Moreover, there are multiple types of join operations according to different join conditions and data relationships with diverse complexities. Because most existing solutions for accelerating the join operation on field programmable gate arrays (FPGAs) focus only on the easiest join application, this study presents a novel architecture that is suitable for multiple types of join operation. This architecture has a modular design and consists of three components that are executed sequentially and in pipeline. Specifically, the top-K sorter is used instead of the full sorter to reduce resource utilization and advance the merge processing. Further, the architecture is perfectly compatible with both N-to-1 and N-to-M join relationships, and can also adapt well to both equi-join and band-join. Experimental results show that this design, which is implemented on an FPGA, achieved a high join throughput of 242.1 million tuples per second, which is better than other reported FPGA implementations.

Real-time sensor signal acquisition poses new challenges in data transmission and storage. Therefore, it is beneficial to insert a lossless compression system between the sensor signal’s generation and subsequent data transmission. Additionally, the compression algorithm must consider both the compression ratio and throughput. This study proposes a two-stage lossless compression system using an integer adaptive predictor to address the inherent data diversity in digital signals and improve the compression ratio. Meanwhile, high-throughput hardware architecture is implemented for the compression system. The experimental results show that our stream-based lossless compression system improves the compression ratio by 10.5%-40.0% compared with the traditional compressor; up to 16.9% compared with the reported stream-based compressor and can operate at a speed of 800MB/s on a field-programmable gate array (FPGA).

The use of sensor applications has been steadily increasing, leading to an urgent need for efficient data compression techniques to facilitate the storage, transmission, and processing of digital signals generated by sensors. Unlike other sequential data such as text sequences, sensor signals have more complex statistical characteristics. Specifically, in every signal point, each bit, which corresponds to a specific precision scale, follows its own conditional distribution depending on its history and even other bits. Therefore, applying existing general-purpose data compressors usually leads to a relatively low compression ratio, since these compressors do not fully exploit such internal features. What is worse, partitioning a bit stream into groups with a preset size will sometimes break the integrity of each signal point. In this paper, we present a lossless data compressor dedicated to compressing sensor signals which is built upon a novel recurrent neural architecture named multi-channel recurrent unit (MCRU). Each channel in the proposed MCRU models a specific precision range of each signal point without breaking data integrity. During compressing and decompressing, the mirrored network will be trained on observed data; thus, no pre-training is needed. The superiority of our approach over other compressors is demonstrated experimentally on various types of sensor signals.

Deep learning models, especially recurrent neural networks (RNNs), have been successfully applied to automatic modulation classification (AMC) problems recently. However, deep neural networks are usually overparameterized, i.e., most of the connections between neurons are redundant. The large model size hinders the deployment of deep neural networks in applications such as Internet-of-Things (IoT) networks. Therefore, reducing parameters without compromising the network performance via sparse learning is often desirable since it can alleviates the computational and storage burdens of deep learning models. In this paper, we propose a sparse learning algorithm that can directly train a sparsely connected neural network based on the statistics of weight magnitude and gradient momentum. We first used the MNIST and CIFAR10 datasets to demonstrate the effectiveness of this method. Subsequently, we applied it to RNNs with different pruning strategies on recurrent and non-recurrent connections for AMC problems. Experimental results demonstrated that the proposed method can effectively reduce the parameters of the neural networks while maintaining model performance. Moreover, we show that appropriate sparsity can further improve network generalization ability.

Join is a data-intensive and compute-intensive operation in database systems. As most existing solutions to accelerate the hash join operation on field programmable gate array (FPGA) are focused on N-to-1 join relationships, their performances rapidly decline on N-to-M joins. To resolve this shortcoming, this study proposes a novel architecture combining hash and sort-merge algorithms for join acceleration. In the build phase, the architecture utilizes a single hash function to build hash tables for two data tables, and the hash collisions are addressed by building ordered linked lists according to their join attributes. In the merge phase, mapped buckets in two hash tables are merged one-to-one to find matching tuples. This architecture lends itself to high parallelism to improve its performance. Experimental results show that the design on a FPGA achieved a high join throughput of 194.0 million tuples per second, which is better than the reported FPGA implementations. Moreover, the architecture is perfectly compatible with both N-to-1 and N-to-M join relationships.

The hash join operator is one of the most important relational operations used in database. The offloading and acceleration of this operation on hardware has been a technique of growing interest for a long time. However, the non-uniform distribution of data caused by hash collisions negatively affects the throughput of the hash join algorithm, owing the variation in the number of hash table accesses required for each lookup. To resolve this issue, a non-collision parallel static random-access memory (SRAM)-based hash join architecture is presented. This architecture utilizes multiple hash functions and content addressable memories (CAMs) to eliminate hash collision, thereby ensuring a worst constant memory access for each phase in the hash join algorithm and consequently improving the hash join throughput. The proposed architecture was implemented on a Xilinx field programmable gate array (FPGA), and the experimental results show that our design achieved a high hash join throughput of 153.6 million tuples per second, and a speedup factor of at least 2.5 with the best existing FPGA-based hash join architecture and a match rate of 50%.