Roberto Canegallo

This paper presents a passive Envelope Detector (ED) to be used for reception of OOK-modulated signals, such as in Wake-Up Receivers employed within Wireless Sensor Networks, widely used in the IoT. The main goal is implementing a temperature compensation mechanism in order to keep the passive ED input resistance roughly constant over temperature, making it a constant load for the preceding matching network and ultimately keeping the overall receiving chain sensitivity constant over temperature. The proposed ED was designed using STMicroelectronics 90 nm CMOS technology to receive 1 kbps OOK-modulated packets with a 433 MHz carrier frequency and a 0.6 V supply. The use of a block featuring a Proportional-to-Absolute Temperature (PTAT) current yields a 5 dB reduction in sensitivity temperature variation across the −40 °C to 120 °C range. Moreover, two different implementations were compared, one targeting minimal mismatch and the other one targeting minimal area. The minimal area version appears to be better in terms of estimated overall chain sensitivity at all temperatures despite a higher sensitivity spread.

This paper presents a readout scheme for Analog In-memory Computing (AIMC) based on an embedded Phase-change Memory (ePCM). Conductance time drift is overcome with a hardware compensation technique based on a reference cell conductance tracking (RCCT). Accuracy drop due to circuits mismatch and variability involved in the computational chain are minimized with an optimized iterative program-and-verify algorithm applied to the PCM devices. The proposed AIMC scheme is designed and manufactured in a 90-nm STMicroelectronics CMOS technology, with the aim of adding a signed Multiply-and-Accumulate (MAC) computation feature to a Ge-rich GeSbTe (GST) embedded PCM array. Experimental characterizations are performed under different operating conditions, and show that mean MAC decrease in time is approximately null at room temperature and reduced by a factor of 3 after 64-hours bake at 85∘C. Based on several MAC operations, the estimated 512×512 Matrix-Vector-Multiplication (MVM) accuracy is 97.4%, whose decrease in time is less than 3% in the worst case.

In this paper, a thorough characterization of phase-change memory (PCM) cells was carried out, aimed at evaluating and optimizing their performance as enabling devices for analog in-memory computing (AIMC) applications. Exploiting the features of programming pulses, we discuss strategies to reduce undesired phenomena that afflict PCM cells and are particularly harmful in analog computations, such as low-frequency noise, time drift, and cell-to-cell variability of the conductance. The test vehicle is an embedded PCM (ePCM) provided by STMicroelectronics and designed in 90-nm smart power BCD technology with a Ge-rich Ge-Sb-Te (GST) alloy for automotive applications. On the basis of the results of the characterization of a large number of cells, we propose an iterative algorithm to allow multi-level cell conductance programming, and its performances for AIMC applications are discussed. Results for a group of 512 cells programmed with four different conductance levels are presented, showing an initial conductance spread under 6%, relative current noise less than 9% in most cases, and a relative conductance drift of 15% in the worst case after 14 h from the application of the programming sequence.

This article presents a data-startable baseband logic featuring a gated oscillator clock and data recovery (GO-CDR) circuit for nanowatt wake-up and data receivers (WuRxs). At each data transition, the phase misalignment between the data coming from the analog front-end (AFE) and the clock is cleared by the GO-CDR circuit, thus allowing the reception of long data streams. Any free-running frequency mismatch between the GO and the bitrate does not limit the number of receivable bits, but only the maximum number of equal consecutive bits (N_m). To overcome this limitation, the proposed system includes a frequency calibration circuit, which reduces the frequency mismatch to ±0.5%, thus enabling the WuRx to be used with different encoding techniques up to N_m = 100. A full WuRx prototype, including an always-on clockless AFE operating in subthreshold, was fabricated with STMicroelectronics 90 nm BCD technology. The WuRx is supplied with 0.6 V, and the power consumption, excluding the calibration circuit, is 12.8 nW during the rest state and 17 nW at a 1 kbps data rate. With a 1 kbps On-Off Keying (OOK) modulated input and −35 dBm of input RF power after the input matching network (IMN), a 10⁻³ missed detection rate with a 0 bit error tolerance is measured, transmitting 63 bit packets with the N_m ranging from 1 to 63. The total sensitivity, including the estimated IMN gain at 100 MHz and 433 MHz, is −59.8 dBm and −52.3 dBm, respectively. In comparison with an ideal CDR, the degradation of the sensitivity due to the GO-CDR is 1.25 dBm. False alarm rate measurements lasting 24 h revealed zero overall false wake-ups.

This paper presents the X-Hall sensor, a viable sensing architecture for implementing a silicon-integrated, broadband, current/magnetic sensor. The X-Hall sensor overcomes the bandwidth limit of the state-of-the-art Hall sensors by replacing the spinning-current technique with DC-biased-based, passive offset compensation. In this way, the X-Hall architecture removes the methodological bandwidth limit due to the spinning-current technique and allows for exploiting the Hall probe up to its practical limit, which is set by the parasitic capacitive effects. Moreover, the X-Hall architecture allows to push the practical bandwidth limit at higher frequencies due to both the removal of the switches inherent in the spinning-current approach and a specifically designed analog front-end. To this end, a differential-difference current-feedback amplifier (DDCFA) is proposed as analog front-end in the X-Hall sensor. A prototype of the proposed X-Hall architecture is implemented in BCD 0.16-μm silicon technology to experimentally assess the performance of the X-Hall architecture. The passive offset compensation implemented into the X-Hall architecture is frequency independent and preserves an adequate offset reduction performance, though less efficient than the spinning-current technique operated at low frequency. Experimental dynamic tests on the prototype identify the presence of an additive parasitic dynamic perturbation due to the package that prevents from fully exploiting the X-Hall prototype up to its designed bandwidth limit. However, the implementation of a post de-emphasis digital filter allows to mitigate for the dynamic perturbation and to experimentally achieve a sensor bandwidth of 4 MHz, which is the broadest bandwidth ever demonstrated by a purely Hall-effect based sensor.

We present a self-sustained battery-less multi-sensor platform with RF harvesting capability down to −17 dBm and implementing a standard DASH7 wireless communication interface. The node operates at distances up to 17 m from a 2 W UHF carrier. RF power transfer allows operation when common energy scavenging sources (e.g., sun, heat, etc.) are not available, while the DASH7 communication protocol makes it fully compatible with a standard IoT infrastructure. An optimized energy-harvesting module has been designed, including a rectifying antenna (rectenna) and an integrated nano-power DC/DC converter performing maximum-power-point-tracking (MPPT). A nonlinear/electromagnetic co-design procedure is adopted to design the rectenna, which is optimized to operate at ultra-low power levels. An ultra-low power microcontroller controls on-board sensors and wireless protocol, to adapt the power consumption to the available detected power by changing wake-up policies. As a result, adaptive behavior can be observed in the designed platform, to the extent that the transmission data rate is dynamically determined by RF power. Among the novel features of the system, we highlight the use of nano-power energy harvesting, the implementation of specific hardware/software wake-up policies, optimized algorithms for best sampling rate implementation, and adaptive behavior by the node based on the power received.