Bin Wang
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Research Subjects
Research Interests
Bin Wang has a total of 13 co-authors. Here are the top co-authors by number of shared publications:
D. Flandre
Institute of Information and Communication Technologies, Electronics and Applied Mathematics (ICTEAM), Université Catholique de Louvain 2 , 1348 Ottignies-Louvain-la-Neuve, Belgium
1 shared publication- Denis Flandre
Université Catholique de Louvain (UCLouvain)
1 shared publication - Iman Sabri Alirezaei
TE Connectivity, Berlin, Germany
1 shared publication - Jean-Pierre Raskin
Université catholique de Louvain
1 shared publication M. Bouterfa
Institute of Information and Communication Technologies, Electronics and Applied Mathematics (ICTEAM), Université Catholique de Louvain 2 , 1348 Ottignies-Louvain-la-Neuve, Belgium
1 shared publicationMohammad Wasil Malik
ICTEAM Institute, Université catholique de Louvain, Belgium
1 shared publication
Latest Publications
- 1 June 2021
- Published by AIP Publishing in Journal of Applied Physics
- Vol. 129 (21) , 214501
The shift of breakdown voltage for silicon membrane strip detectors resulting from surface avalanche
Silicon membrane strip photodetectors are fabricated based on thin silicon-on-insulator (SOI) wafers. The thin SOI wafer is realized by exploiting a thinning process on backside. Such detectors can be implemented in proton-beam position detection because its ultra-thin membrane substrate can reduce beam scattering and offer the considerable advantages of higher radiation hardness. A p-spray implantation process is typically performed at the silicon surface between the -strips in order to insulate them, without requiring an extra photolithographic mask. In this paper, the sources of leakage current in the detector are first studied by considering both activation energy and simulation analysis in Silvaco TCAD. While the device is operating below avalanche breakdown voltage, the Shockley–Read–Hall process and trap-assisted-tunneling process are dominantly contributing to leakage current. The dominant breakdown voltage is attributed to the premature breakdown in the junction of region. The shift of this breakdown voltage under repeated avalanche processes is analyzed in-depth by both experiments and simulations, as a function of temperature and electrical stress conditions, which are introducing an important reliability problem. The electrical stress can be attributed to an increase in fixed charge density at the Si/ interface. The breakdown voltage finally increases by 4 V after successive avalanche breakdowns as a function of the applied excess bias voltage beyond breakdown voltage.- 1 June 2021
- Published by AIP Publishing in Journal of Applied Physics
- Vol. 129 (21) , 214501
The shift of breakdown voltage for silicon membrane strip detectors resulting from surface avalanche
Silicon membrane strip photodetectors are fabricated based on thin silicon-on-insulator (SOI) wafers. The thin SOI wafer is realized by exploiting a thinning process on backside. Such detectors can be implemented in proton-beam position detection because its ultra-thin membrane substrate can reduce beam scattering and offer the considerable advantages of higher radiation hardness. A p-spray implantation process is typically performed at the silicon surface between the -strips in order to insulate them, without requiring an extra photolithographic mask. In this paper, the sources of leakage current in the detector are first studied by considering both activation energy and simulation analysis in Silvaco TCAD. While the device is operating below avalanche breakdown voltage, the Shockley–Read–Hall process and trap-assisted-tunneling process are dominantly contributing to leakage current. The dominant breakdown voltage is attributed to the premature breakdown in the junction of region. The shift of this breakdown voltage under repeated avalanche processes is analyzed in-depth by both experiments and simulations, as a function of temperature and electrical stress conditions, which are introducing an important reliability problem. The electrical stress can be attributed to an increase in fixed charge density at the Si/ interface. The breakdown voltage finally increases by 4 V after successive avalanche breakdowns as a function of the applied excess bias voltage beyond breakdown voltage.- 8 January 2021
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 68 (2) , 892-898
A Physical Model of Contact Resistance in Ti-Contacted Graphene-Based Field Effect Transistors
The effect of device fabrication processing conditions is often overlooked in the evaluation of the contact resistance in metal–graphene contact. In this work, we investigate the Ti–graphene contact resistance theoretically and experimentally. A compact model has been proposed to reveal and evaluate the role of different factors in controlling the value of contact resistance. A layer of oxidized Ti or polymer residues at the Ti–graphene interface has been considered to explain the reduced carrier transmission probability through the interface. Experimental results report a low contact resistance as small as 271.45 $\Omega ~\cdot \mu \text{m}$ and our model agrees with the measured values. The proposed model explains the large variation of the contact resistance reported in the literature up to date and help to improve metal–graphene contact for future applications.
- 8 January 2021
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 68 (2) , 892-898
A Physical Model of Contact Resistance in Ti-Contacted Graphene-Based Field Effect Transistors
The effect of device fabrication processing conditions is often overlooked in the evaluation of the contact resistance in metal–graphene contact. In this work, we investigate the Ti–graphene contact resistance theoretically and experimentally. A compact model has been proposed to reveal and evaluate the role of different factors in controlling the value of contact resistance. A layer of oxidized Ti or polymer residues at the Ti–graphene interface has been considered to explain the reduced carrier transmission probability through the interface. Experimental results report a low contact resistance as small as 271.45 $\Omega ~\cdot \mu \text{m}$ and our model agrees with the measured values. The proposed model explains the large variation of the contact resistance reported in the literature up to date and help to improve metal–graphene contact for future applications.