Jong Keuk Park

Neuromorphic computing research is being actively pursued to address the challenges posed by the need for energy-efficient processing of big data. One of the promising approaches to tackle the challenges is the hardware implementation of spiking neural networks (SNNs) with bio-plausible learning rules. Numerous research works have been done to implement the SNN hardware with different synaptic plasticity rules to emulate human brain operations. While a standard spike-timing-dependent-plasticity (STDP) rule is emulated in many SNN hardware, the various STDP rules found in the biological brain have rarely been implemented in hardware. This study proposes a CMOS-memristor hybrid synapse circuit for the hardware implementation of a Ca ion-based plasticity model to emulate the various STDP curves. The memristor was adopted as a memory device in the CMOS synapse circuit because memristors have been identified as promising candidates for analog non-volatile memory devices in terms of energy efficiency and scalability. The circuit design was divided into four sub-blocks based on biological behavior, exploiting the non-volatile and analog state properties of memristors. The circuit was designed to vary weights using an H-bridge circuit structure and PWM modulation. The various STDP curves have been emulated in one CMOS-memristor hybrid circuit, and furthermore a simple neural network operation was demonstrated for associative learning such as Pavlovian conditioning. The proposed circuit is expected to facilitate large-scale operations for neuromorphic computing through its scale-up.

Various memristive devices have been proposed for use in neuromorphic computing systems as artificial synapses. Analog synaptic devices with linear conductance updates during training are efficiently essential to train neural networks. Although many different analog memristors have been proposed, a more reliable approach to implement analog synaptic devices is needed. In this study, we propose the memristor of a Cu/SiO_x/implanted a-SiGe_x/p⁺⁺ c-Si structure containing an a-Si layer with properly controlled conductance through Ge implantation. The a-SiGe_x layer plays a multifunctional role in device operation by limiting the current overshoot, confining the heat generated during operation and preventing the silicide formation reaction between the active metal (Cu) and the Si bottom electrode. Thus, the a-SiGe_x interface layer enables the formation of multi-weak filaments and induces analog switching behaviors. The TEM observation shows that the insertion of the a-SiGe_x layer between SiO_x and c-Si remarkably suppresses the formation of copper silicide, and reliable set/reset operations are secured. The origin of the analog switching behaviors is discussed by analyzing current-voltage characteristics and electron microscopy images. Finally, the memristive-neural network simulations show that our developed memristive devices provide high learning accuracy and are promising in future neuromorphic computing hardware.

In this paper, we propose a novel Poisson process generator that uses multiple thermal noise amplifiers (TNAs) as a source of randomness and controls its event rate via a frequency-locked loop (FLL). The increase in the number of TNAs extends the effective bandwidth of amplified thermal noise and hence enhances the maximum event rate the proposed architecture can generate. Verilog-A simulation of the proposed Poisson process generator shows that its maximum event rate can be increased by a factor of 26.5 when the number of TNAs increases from 1 to 10. In order to realize parallel stochastic simulations of the biochemical reaction network, we present a fundamental reaction building block with continuous-time multiplication and addition using an AND gate and a 1-bit current-steering digital-to-analog converter, respectively. Stochastic biochemical reactions consisting of the fundamental reaction building blocks are simulated in Verilog-A, demonstrating that the simulation results are consistent with those of conventional Gillespie algorithm. An increase in the number of TNAs to accelerate the Poisson events and the use of digital AND gates for robust reaction rate calculations allow for faster and more accurate stochastic simulations of biochemical reactions than previous parallel stochastic simulators.

A synaptic device that contains weight information between two neurons is one of the essential components in a neuromorphic system, which needs highly linear and symmetric characteristics of weight update. In this study, a charge trap flash (CTF) memory device with a multilayered high-κ barrier oxide structure on the MoS₂ channel is proposed. The fabricated device was oxide-engineered on the barrier oxide layers to achieve improved synaptic functions. A comparison study between two fabricated devices with different barrier oxide materials (Al₂O₃ and SiO₂) suggests that a high-κ barrier oxide structure improves the synaptic operations by demonstrating the increased on/off ratio and symmetry of synaptic weight updates due to a better coupling ratio. Lastly, the fabricated device has demonstrated reliable potentiation and depression behaviors and spike-timing-dependent plasticity (STDP) for use in a spiking neural network (SNN) neuromorphic system.