Vishnupriya Shivakumar

A true random number generator (TRNG) is crucial to support information security in IoT devices. Conventional RO-based TRNGs depend on intrinsic jitter as an entropy source. It remains vulnerable to environmental and malicious attacks, such as temperature manipulation and frequency injection, which degrade randomness and compromise security. To address these issues, the proposed design integrates a Galois-based conditioning mechanism that enhances entropy quality by reducing bias and correlation through structured XOR feedback. The TRNG is implemented with two cascaded inverters (TSI) as a ring oscillator and a Galois inverter as an extrinsic jitter, named the Galois jitter ring oscillator (GJRO). Additionally, the time-variant XOR is used for tapping bits and acts as a random switch between oscillatory and Galois states for implementing a true source of randomness in the entropy. Experimental analyses are demonstrated in SilTerra 0.13 µm with low power of 46.4 pW, area of 129.61 〖µm〗^2, and high throughput of 2.9 Gbps. The hybrid reconfigurable strategy allows the source to generate faster random bits per clock cycle in the range of 12.8 Gbps for a 2^7 parallel GJRO implementation. The random sequences are evaluated using statistical test suites including NIST SP 800-22 along with entropy estimation and autocorrelation analysis. Consequently, the entropy source is tested for its robustness against frequency injection attacks in a voltage range of 0.6V to 1.2V and a temperature range of 0 °C to 100 °C. Furthermore, the generated bitstreams are introduced into a regression-based machine language model to monitor statistical features and identify deviations from normal behaviour, thereby enabling real-time attack detection.

A test pattern generator generates a pseudorandom test pattern that can be weighted to reduce the fault coverage in a built-in self-test. The objective of this paper is to propose a new weighted TPG for a scan-based BIST architecture. The motivation of this work is to generate efficient weighted patterns for enabling scan chains with reduced power consumption and area. Additionally, the pseudo-primary seed of TPG is maximized to obtain a considerable length in the weighted pseudorandom patterns. The maximum-length weighted patterns are executed by assigning separate weights to the specific scan chains using a weight-enabled clock. This approach reduces the hardware overhead and achieves a low power consumption of 26.7 nW. Moreover, the proposed weighted TPG is applied in two different test-per-scan BIST architectures and achieves accurate results. The weighted patterns are also generated with fewer switching transitions and higher fault coverages of 98.81% and 97.35% in two different BIST architectures. This process is observed with six other circuits under test as their scan chains. The simulation results are tested with a SilTerra 0.13 μm process on the Mentor Graphics IC design platform. Furthermore, the proposed weighted TPG is enlarged to a higher bit TPG, which is compared to accomplish the performance strategies. The experimental results of the proposed TPG design are compared and tabulated with existing potential TPG designs.