Mohamed Dessouky

A precision bandgap reference (BGR) is an essential building block in modern analog and mixed-signal systems, as it provides stable and predictable current and voltage references required for reliable operation across process, voltage, and temperature variations. However, one of the key challenges in conventional BGR circuits is their sensitivity to resistance variations, which directly impacts the accuracy of bias currents. Even small changes in resistance can lead to significant current mismatch between the core branches of the circuit, thereby degrading output stability and limiting the precision of the overall system. This degradation is particularly problematic in high-performance applications such as data converters, oscillators, and low-power biasing networks, where robust current matching is critical. To address this limitation, this work proposes a resistance-compensated BGR architecture that incorporates an auxiliary trimming network and a compensation branch. The trimming network senses variations in resistance and generates a control bias proportional to the deviation, while the compensation branch injects a corrective current into the output stage. By dynamically balancing the mismatch introduced by resistor spread, the proposed architecture effectively restores current stability across process corners. This method achieves reduction in the current variation across resistance corners from 21% to 3% in worst-case corners (±3%). This approach offers enhancement of current mismatches in analog systems in which robust current is essential.

Real Number Modelling (RNM) has become more common as a part of mixed-signal SoC validation. The paper illustrates modelling Phase Locked Loops (PLL) using SystemVerilog-Real Number Modelling (SV-RNM) as it’s one of the essential blocks in any Integrated Circuit (IC) and a feedback loop system. It uses the Piece-Wise Linear (PWL) technique to model the loop filter with higher orders, higher than a first order LPF. The PWL technique needs both the value and the slope information so that the values between the samples can be interpolated, this is represented by User-Defined Type (UDT) and Net (UDN). A fractional divider is modelled using the Sigma-Delta modulator of the MASH 1-1-1 topology to generate the fractional part. Modelling non-linear effects like the phase noise of each sub-block, which is converted to the RMS-jitter (seconds), by using the ‘class’ datatype that takes complex variables of real and imaginary values then returns some functionalities on these complex variables. Moreover, the loading effect due to capacitances and resistances at the output using User-Defined Resolved Nets (UDRN). The simulation results ensure that the accuracy improvement in the expected PLL outputs compared to the outputs from the transistor level with a much faster simulation time as an event-driven simulator is used.

This paper proposes a resolution control loop that runs in background to control the time resolution of a mid-rise Time to Digital Converter (TDC) used as a phase detector in All-Digital Phase Locked Loops (ADPLLs). The proposed resolution control loop minimizes the TDC resolution until the TDC linear dynamic range equals the range of the input time error. Consequently, PLL in-band phase noise is reduced due to reduction of the Power Spectral Density (PSD) of the TDC quantization noise. Moreover, the linearity of the TDC transfer function across the range of the input time error is guaranteed. On contrary, the counterpart resolution control loop based on Lloyd-Max algorithm does not guarantee the linearity of the TDC transfer function across the range of the input time error. Furthermore, the proposed resolution control loop achieves TDC quantization noise with a lower variance compared to that achieved by the counterpart resolution control loop when applied with a TDC with more than 3 bits. Finally, the hardware implementation of the proposed resolution control loop is more area and power efficient compared to the implementation of the counterpart resolution control loop.

Dynamic power is a major source of power dissipation for high speed designs. Domain isolation methodology is a recently-proposed technique for reducing dynamic power based on controlling the evaluation phase of dynamic logic (toggling control). This work demonstrates some design issues in the domain isolation methodology and explains why it is inefficient with pipelined systems. We propose fixes for its identified issues, which enables using the toggling control with pipelined systems in a more efficient way. A novel flow named ``Power Reduction Flow'' is proposed for reducing dynamic power of digital circuits. Our flow uses novel design analytical methods, novel ``Dynamic Logic Modifier Flow'', and novel ``Dynmic Logic Area Validation Flow'' for reducing dynamic power with conditionally improving performance. The new design analytical methods are based on probability theory, SystemVerilog covergroups, and digital circuit modeling. A new event type perspective is also proposed to analyze designs to reduce dynamic power in them. Experimental results using TSMC 65 nm and low supply voltages show up to 59% power reduction compared to the original traditional techniques with improving circuit's performance by 3x of its original maximum operating frequency at the cost of an extra 12.3% increase in area.

Electrostatic discharge (ESD) robustness is an extremely important aspect in integrated circuits (ICs), and is well established for regular 2D ICs. However, 2.5D and 3D integration present new challenges in both design and verification. While several studies have focused on design methodologies to achieve effective ESD protection in 2.5D and 3D ICs, there is a lack of research into automated ESD verification solutions for these technologies. Therefore, this paper focuses on automated ESD verification in 2.5D and 3D ICs. We explain the verification challenges introduced by these integration technologies, and propose an automated ESD verification methodology for 2.5D and 3D ICs. We implement this methodology in a programmable checker to automate the verification for complete 2.D and 3D IC designs. The checker differentiates between external and internal inputs/outputs from the assembly level without the use of layout markers on the die level. It checks for correct, incorrect, and missing ESD protection circuitries for each category of inputs/outputs. It checks total parasitic resistance and performs current density analysis for the relevant interconnect routes through the entire 3D IC design layout to ensure these routes can sustain the ESD event. We apply our proposed checker to a test case that includes 2.5D and 3D-specific ESD challenges, and demonstrate its effectiveness.