Zheyu Yan

Compute-in-memory (CiM) offers a promising solution to the hardware challenges faced in artificial intelligence (AI) and the Internet of Things (IoT), particularly in tackling the “memory wall” problem. By leveraging non-volatile memory (NVM) devices arranged in a crossbar structure, CiM efficiently accelerates multiply-accumulate (MAC) computations, which are essential for neural networks and various AI models. Emerging NVM, i.e., Ferroelectric FET (FeFET), is a particularly appealing choice for constructing ultra-low-power CiM arrays due to its CMOS compatibility, voltage-driven write/read mechanisms and high I _ON /I _OFF ratio. Operating FeFETs in the subthreshold region, i.e., subthreshold-FeFETs, further reduces power, but introduces vulnerability to temperature drift, leading to potential accuracy degradation. In this article, we present subthreshold-FeFET based temperature-resilient 2T-1FeFET and 2FeFET-1T CiM cell designs that address the temperature vulnerability. These two cells leverage feedback mechanisms to minimize the output current fluctuations caused by temperature drift. We further propose GTRCiM, a novel generic temperature-resilient CiM design that accommodates both our proposed CiM cells and other typical FeFET based cells while maintaining ultra-low-power consumption with subthreshold-FeFETs. By incorporating an additional column of the CiM array as a reference, and leveraging the temperature-resilient cell design, GTRCiM compensates for the effects of temperature drift, as temperature affects both arrays uniformly. We integrate the proposed GTRCiM array with typical 1FeFET-1R, and our proposed 2T-1FeFET, 2FeFET-1T cells and validate that GTRCiM enhances the temperature resilience with our proposed cells and even the temperature vulnerable 1FeFET-1R cell. Benchmarking results at system level using the NeuroSim framework show that our proposed GTRCiM array integrated with subthreshold-FeFET based 1FeFET-1R cells achieves 28.09 TOPS/W energy efficiency, surpassing existing CiM designs while maintaining sufficient temperature resilience.

Analog circuits exhibit rich structural diversity and intricate interconnections across various functional types. Such complexity severely limits scalable automation. Existing rule-based and graph learning approaches struggle to generalize across unseen circuit topologies or high- precision hierarchical recognition. To address these challenges, we propose GEFT (Generative Eulerian Family Transformer), a transformer framework for comprehensive hierarchical analog circuit understanding. GEFT introduces an Eulerian-family-based graph representation that establishes a reversible and lossless mapping between circuit topology and sequential models, enabling efficient structure-aware analysis. The model unifies hierarchical understanding from subcircuit recognition to full circuit topology classification within the same transformer backbone, achieving robust generalization across more than 13 categories of 3350 diverse analog circuits. Experimental results demonstrate that GEFT attains 98.24% accuracy in subcircuit recognition and 91.42% accuracy in topology classification, providing a scalable and interpretable foundation for analog circuit design automation.

Large language models (LLMs) have been the driving force behind significant advancements in artificial intelligence. However, their unique self-attention mechanism leads to difficulties in accelerating the inference. Softmax, with its complex nonlinear operations and low parallelism, significantly limits the efficiency of LLMs for long sequences. This work proposes a novel high-parallelism hardware/software co-design Softmax solution. By incorporating a sum estimation algorithm, we eliminate the need for complex exponential on all elements. A high-speed low-energy hardware architecture is introduced by applying high-parallelism statistical module and simplified division module. Experimental results demonstrate that our approach achieves a 9.90–44.75% reduction in latency and up to a 17.36% reduction in energy consumption compared with state-of-the-art Softmax hardware, with minimal impact on model inference accuracy.

As VLSI designs grow increasingly complex and transition to smaller process nodes, accurate and efficient library characterization has become essential for modern design workflows. Existing open-source tools are often constrained by limited functionality, efficiency, and accuracy, making them insufficient for today’s design challenges. This article reviews the shortcomings of current open-source tools and introduces ZlibBoost, a novel open-source framework designed to provide both flexibility and high performance. Its modular, front-end and back-end separated architecture, along with user-friendly interfaces, enables seamless customization, integration of machine learning models, and expanded simulator compatibility. A variety of key features are introduced to significantly enhance both accuracy and efficiency of library characterization. Experimental results demonstrate ZlibBoost’s capability to meet the demands of both academic research and practical applications, establishing it as a robust solution for advancing semiconductor design.