Jung-Gyun Kim

Integrating on-device learning into autonomous systems requires neural network frameworks that achieve both high energy efficiency and low latency. While spiking neural networks (SNNs) provide a promising event-driven paradigm, implementing hardware-efficient learning remains a challenge due to the computational overhead of error signaling and global gradients. This paper introduces a hardware-oriented hierarchical spiking predictive coding (SPC) framework designed for end-to-end event-driven systems. The proposed architecture implements an implicit prediction error encoding mechanism through local lateral and supervisory feedback connections, eliminating the need for dedicated error-storage memory or complex inter-layer error communication. The entire framework is structured and parameterized for physical implementation, utilizing digital-aligned simulations and arithmetic operations. We evaluate the system on neuromorphic datasets using a fixed 1 ms temporal resolution to mirror real-time hardware constraints. Experimental results demonstrate that the SPC framework can effectively identify stimuli from transient event streams, achieving stable on-device learning. Our work provides a practical path toward deploying low-power, scalable hierarchical spiking networks in resource-constrained environments.

To date, pixel noise in a dynamic vision sensor (DVS) has not been accurately analyzed in the literature, and its optimization has been performed empirically. This paper presents a theoretical analysis of the DVS pixel noise. The mean-squared noise voltage at the pixel output from each noise source in a pixel is mathematically derived and verified based on simulations and measurements. A design method to determine the pixel bias currents for a given photocurrent is also presented based on the noise analysis to improve noise performance while maintaining pixel latency. A prototype DVS chip was fabricated in a 110 nm complementary metal-oxide-semiconductor image sensor process and tested under various light and pixel bias conditions. It is shown that the proposed noise analysis and design method successfully predicted the noise performance of the DVS chip.

This study proposes self-calibration of capacitor mismatch errors for high-resolution pipeline analog-to-digital converters (ADCs). The proposed calibration circuit recursively amplifies the capacitor mismatch error by re-utilizing a multiplying digital-to-analog converter in a pipeline stage without increasing the circuit complexity, and the amplified error voltage is converted into digital code by utilizing the remaining pipeline stages. Error correction is performed by subtracting the digital code from the ADC output during normal operation. A prototype of a 12-bit pipeline ADC is fabricated in a 0.18 µm standard CMOS process. The ADC comprises eight 1.5-bit stages, followed by a 4-bit flash ADC as the final stage; the capacitor mismatch errors in the first two pipeline stages are corrected by utilizing the proposed self-calibration technique. Although the calibration method is employed in a 1.5-bit stage architecture, which uses a gain-of-two switched-capacitor amplifier, it is applicable to different bit-per-stage architectures. The ADC linearity significantly improves after calibration, and this is verified through simulations and measurements.

This paper presents the design and fabrication of a low-power incremental delta-sigma analog-to-digital converter (ADC) with an adaptive bias technique suitable for complimentary metaloxide semiconductor (CMOS) image sensors (CISs). The adaptive biasing circuitry provides the amplifier with a predicted minimum current value required for the integrator output to settle; this optimized current flows through the amplifier and reduces power consumption by 40%. A prototype ADC fabricated using a 0.18 μm CMOS process, achieves an SNDR of 65 dB at a sampling frequency of 25 MHz and consumes 13.5 μW from a 1.8 V power supply. The measured differential and integral nonlinearities are +0.31/-0.42 and +0.62/-0.75 at a 12-bit accuracy, respectively.

This study proposes self-calibration of capacitor mismatch errors for high-resolution pipeline analog-to-digital converters (ADCs). The proposed calibration circuit recursively amplifies the capacitor mismatch error by re-utilizing a multiplying digital-to-analog converter in a pipeline stage without increasing the circuit complexity, and the amplified error voltage is converted into digital code by utilizing the remaining pipeline stages. Error correction is performed by subtracting the digital code from the ADC output during normal operation. A prototype of a 12-bit pipeline ADC is fabricated in a 0.18 µm standard CMOS process. The ADC comprises eight 1.5-bit stages, followed by a 4-bit flash ADC as the final stage; the capacitor mismatch errors in the first two pipeline stages are corrected by utilizing the proposed self-calibration technique. At a sampling rate of 30 MS/s, the measured differential and integral nonlinearities improve from +0.82/-0.75 and +1.12/-1.79 to +0.45/-0.41 and +0.47/-0.91 after calibration, respectively. Further, the measured dynamic performances improve significantly with calibration. For an input frequency of 2.09 MHz, the ADC achieves a spurious-free dynamic range (SFDR) and signal-to-noise and distortion ratios (SNDR) of 69.3dB and 63.9dB before calibration, respectively. After calibration, the SFDR and SNDR increase to 84.1dB and 68.9dB, respectively, and the effective number of bits is approximately 11.1bit. The power consumption of the ADC is 35mW under 1.8V supply, and the resulting figure of merit is 514fJ/conversion step.

A hardware-efficient implementation of a spiking cooperative network (SCN) for a real-time event-based stereo correspondence system is presented. While fully utilizing the advantage of event data, the proposed SCN design significantly reduces the amount of hardware resources by utilizing distinct properties of the SCN, such as the repeatability of synaptic connections and operations, through physical constraints. A stereo system consisting of a field-programmable gate array (FPGA) and a pair of dynamic vision sensors (DVSs) is implemented to demonstrate the SCN design. Stereo livestreamed event data are generated from the DVSs, and the SCN is implemented on an FPGA chip to process the event data. The SCN system has four cores, each comprising an array of 32 Coincidence-Disparity units that calculate the 32-level disparity in a semi-parallel manner. The system performance was evaluated experimentally to estimate the depth of objects moving at different speeds. A rotating drum with a diameter of 8 cm was used in the test. The median relative error of the estimated depth at a rotation speed of 16.7 Hz ranged from 7.3% to 10.6%.

A CMOS image sensor (CIS) that can perform on-chip binary convolution is presented. The CIS can greatly reduce memory usage and computational complexity by directly generating a feature map for a binary neural network. The pixel readout of the CIS is performed in the column-parallel fashion using incremental delta-sigma analog-to-digital converters (ADCs). The CIS operates in two different modes: convolution and normal modes. When the column ADC is working in the convolution mode, it works as a first-order delta-sigma ADC and generates convolved images using a binary kernel. In the normal operation mode, the ADC is switched to a second-order delta-sigma ADC with little hardware modification and used to capture high-quality images. To demonstrate the CIS architecture, a 192 × 128-pixel CIS, which occupies an active die area of 14.44 mm ² , is fabricated in a 0.18 μm standard CMOS process. The performance of the CIS is evaluated through measurements and network simulations. In the normal operation mode, the CIS achieves a read noise of 14.79 e ^- _rms and a full-well capacity of 6,420 e ^- with a resulting dynamic range of 53 dB. The power consumptions of the CIS are 49.2 and 52.5 mW during the normal and convolution modes, respectively.