Wen Liu

We report the successful realization of a room-temperature blue GaN photonic crystal surface-emitting laser (PCSEL) diode fabricated using a regrowth-free approach. By employing a square lattice photonic crystal structure with modified triangular air holes, we achieve robust two-dimensional single-mode lasing. The device operates with a threshold current density of 5.2 kA/cm2 and emits a Gaussian-shaped beam with exceptionally low beam divergence, measured at 1.15 mrad (0.066°). Furthermore, the symmetry-breaking nature of the triangular air holes enforces a stable linear polarization perpendicular to the long edge of the triangle. This work demonstrates that high-beam-quality blue PCSELs can be achieved using non-regrowth fabrication processes with simple hole geometry, paving the way for high-performance blue laser sources.

Conventional electronics for extreme environments are typically restricted to single thermal regimes, limiting the feasibility of monolithic circuits capable of wide-range operation. To address this, this letter reports a monolithic voltage reference implemented in D/E-mode p-GaN HEMT technology for operation from -269 °C (5 K) to 250 °C. Based on impedance analysis of the conventional two-transistor reference, a multi-loop topology utilizing depletion-mode devices is introduced to suppress output line sensitivity and improve interference immunity. Experimental characterization demonstrates a stable 1.45 V output across a wide supply range of 5–56 V, achieving a line sensitivity of 0.003421 %/V and a power supply rejection of -50.46 dB at 100 Hz. These results establish the feasibility of high-stability biasing for monolithic all-GaN systems under extreme thermal conditions.

A monolithically integrated gallium nitride (GaN) hysteresis comparator based on complementary logic (CL) architecture is demonstrated on a GaN-on-Si platform. The proposed circuit integrates a first-stage comparator, a second-stage inverter buffer, and a feedback network to generate a hysteresis window. At V _DD = 6 V, the fabricated hysteresis comparator achieves an output swing of ∼5.8 V and a hysteresis window of ∼1.5 V. Transient voltage waveforms at critical circuit nodes are measured and analyzed to elucidate the impact of GaN n/p-channel field-effect transistor (n/p-FET) performance mismatch on circuit operation. The analysis reveals that the low current density and threshold voltage shifts of p-FETs limit the switching precision and slew rate. Based on these findings, strategies for performance enhancement are identified from both device processing and circuit design perspectives. These results provide valuable insights for the further development of GaN CL integrated circuits for next-generation power conversion systems.

AlGaN/GaN high electron mobility transistors (HEMTs) with an AlN back barrier have shown significant potential in high-voltage and high-frequency applications. However, achieving an ultra-thin and smooth GaN channel layer on AlN templates is challenging due to large lattice mismatch, as the mismatch-induced compressive strain inevitably results in surface roughening during GaN growth. Herein, a temperature-variable GaN growth strategy featuring continuous source supply is proposed to balance the strain and surface morphology. Specifically, intentionally rough low-temperature GaN is first employed to suppress uncontrolled compressive strain relaxation in pseudomorphic growth, and then ultra-thin GaN grown at high temperature can recover the surface morphology. It is crucial that the GaN growth be uninterrupted during the temperature increase process, which protects the surface from GaN decomposition. As such, a root mean square roughness of 0.74 nm in a 10 × 10 μm2 area is realized at a GaN thickness of 160 nm, laying a solid foundation for the stacking of an AlGaN/GaN/AlN heterostructure featuring an ultra-thin GaN channel layer. Eventually, the fabricated HEMTs exhibit a high breakdown voltage of 2300 V and an ON/OFF current ratio of 109. This study provides a feasible solution for stacking AlGaN/GaN/AlN HEMTs featuring an ultra-thin and smooth GaN channel layer, and accelerates their practical application.

This article reports the monolithic integration of gallium nitride (GaN)-based complementary logic (CL) circuits using MIS-gated $p$ / $n$ -FETs on a $p$ -GaN/UID-GaN/AlGaN/GaN platform. By employing a bilayer gate dielectric stack (2 nm PEALD AlON/18 nm ALD Al₂O ${}_{{3}}\text {)}$ , the MIS-gated $n$ -FET achieves enhanced gate breakdown and negligible leakage over a wide ${V}_{\text {GS}}$ range (−2 to 10 V). Time-dependent dielectric breakdown (TDDB)-based lifetime modeling predicts a maximum operating ${V}_{\text {GS}}$ of 6.75V for 10-year reliability. Furthermore, the optimized $p$ -FET exhibits a high ${I}_{\mathrm {on}}$ / ${i} _{\mathrm {off}}$ ratio exceeding $10^{{8}}$ , an enhancement-mode (E-mode) threshold voltage ( ${V}_{\text {TH}}\text {)}$ of −0.5 V, and a peak ${I}_{\mathrm {on}}$ of 10.6 mA/mm. The resulting GaN-based CL inverter demonstrates a large 11-V gate swing, rail-to-rail output, and well-matched $n$ / $p$ -FET current density, offering a robust solution for GaN-based power integrated circuit (IC) integration.

Owing to the lack of high-quality thick oxides formed by in situ oxidation, gallium nitride (GaN) trench MOSFETs are subject to pronounced electric field crowding at the trench bottom corners, which limits their off-state blocking capability. In this work, based on a GaN-on-silicon (Si) epitaxy, a thick SiO₂ deposition process was applied to the trench bottom. This approach effectively redistributes the electric field, shifting the field concentration from the dielectric/GaN corners into a 300-nm SiO₂ layer. This terminal structure makes the device breakdown more dependent on the intrinsic blocking capability of GaN rather than on premature electric-field crowding at the trench bottom corners. As a result, a state-of-the-art breakdown voltage of 787 V was achieved for the quasi-vertical structure on a heterogeneous substrate. Furthermore, the device with the thick bottom oxide also exhibits a high threshold voltage (V_th) of 7.6 V, an on/off ratio exceeding $\text{10}^{\text{7}}$ , a specific on-resistance (R ${}_{ \text {on},\text {sp}}$ ) of 3.9 m $\Omega \cdot \text {cm}^{\text{2}}$ , and a Baliga’s figure of merit (BFOM) of 159 MW/ $\text {cm}^{\text{2}}$ , demonstrating the promise of this process for GaN-on-Si trench MOSFETs in future high-power electronics.

This letter demonstrates a fully monolithic pixel platform integrating a micro-light-emitting diode (micro-LED) with a two-transistor-one-capacitor (2T1C) driver circuit. The 2T1C configuration, comprising two AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) and a metal-insulator-metal (MIM) capacitor, is fabricated with the micro-LED on a shared epitaxial structure. The MIS-HEMT shows a high drain current density of 253 mA/mm and a minimal gate leakage current of 100 pA/mm. Leveraging the superior driving capabilities and good gate insulation of the MIS-HEMTs, the 2T1C circuit performs precise control and fast switching operations. A maximum operating frequency of 500 kHz is reached,markedly improving the pixel update rate each frame for display application and the pixel modulation frequency for high-speed visible light communication.

Gallium nitride (GaN)-based transistors with p-type GaN (p-GaN) gates are widely recognized as promising devices for power converter applications, due to their positive and stable threshold voltage, low on-resistance, and high breakdown field. However, the fabrication of p-GaN gate high electron mobility transistors (HEMTs) faces several key process challenges, among which the etching of the p-GaN layer has recently become particularly important. Given the emergence of novel p-GaN etching techniques, a comprehensive review that encompasses scientific classification and systematic evaluation of these methods is essential. This paper aims to fill this gap by reviewing the latest fabrication technologies for forming p-GaN gates in p-GaN/aluminum gallium nitride (AlGaN)/GaN heterojunctions. Firstly, the etching methods are categorized into self-terminating etching, dual-step cyclic etching, and plasma treatment techniques. These three classes are comprehensively summarized and compared in terms of etching rate, mechanisms, selectivity, and applicability. Self-terminated etching methods are divided into oxygen-based and fluorine-based systems, with a focus on the influence of critical process parameters on etch rate and selectivity. Subsequently, repetitive self-limiting etching techniques, including digital etching (DE) and atomic layer etching (ALE), are reviewed, with an emphasis on oxide-chloride and chloride-inert gas systems. Finally, plasma passivation processes are introduced as an alternative approach for achieving enhancement-mode p-GaN gate HEMTs. This paper provides a summary and discussion of the key fabrication process of p-GaN gate devices—namely, the p-GaN cap layer etching engineering. It offers guidance for selecting appropriate etching methods under different application scenarios and provides valuable insights for the future development of GaN HEMTs.