Sree Ranjani Rajendran

The growth of machine learning (ML) and deep learning (DL) has resulted in the rapid development and implementation of dedicated hardware accelerators, including GPUs, TPUs, FPGAs, and custom ASICs. These accelerators maximize performance and efficiency yet present novel hardware level security vulnerabilities that are not well explored. This survey provides a detailed taxonomy of hardware security threats to ML/DL accelerators, grouping them by attacker, system layer, and stage of the ML lifecycle. We conduct a systematic survey of the current defenses and suggest a unified assessment framework. Moreover, we discuss the security aspects of new paradigms like neuromorphic computing and quantum accelerators. Our survey aims to close the gap between optimization of ML performance and hardware-level security assurance, and point out key research gaps and opportunities to design secure ML hardware. It is the first lifecycle-consistent, cross-layer survey that covers GPUs, FPGAs, TPUs, ASICs, edge, and emerging accelerators, offering an unified reference to researchers and practitioners.

As the deployment of photovoltaic (PV) systems accelerates globally, the demand for intelligent, real-time energy management solutions has grown. Digital Twin (DT) technology, which creates dynamic, synchronized virtual replicas of physical PV assets, has proven valuable for monitoring and basic control. However, most current DT-PV implementations are confined to data visualization, fault detection, or offline simulations, lacking capabilities for predictive control, cyber-physical security, and energy storage integration. This survey critically reviews the emerging role of DTs beyond monitoring, focusing on three key areas: (i) predictive control frameworks, including real-time inverter regulation and maximum power point tracking (MPPT) coordination; (ii) cybersecurity mechanisms within DT-enabled PV systems, such as anomaly detection, threat mitigation, and secure IoT protocols; and (iii) integration of battery storage into DT models for state-of-charge estimation and co-optimization. While significant progress is noted in predictive control and grid-interfaced DT applications, the use of DT for guiding MPPT and coordinating energy storage remains in a nascent stage. Using a PRISMA-style review methodology, this survey synthesizes recent advances across PV and related energy domains, this work identifies key gaps, transferable innovations, and outlines a future research roadmap toward scalable, secure, and intelligent DT-PV systems.

Digital twins (DTs) are emerging as transformative tools for the monitoring, control, and optimization of photovoltaic (PV) systems. While prior studies have addressed aspects such as MPPT (Maximum Power Point Tracking), forecasting, and inverter control in isolation, a cohesive, system-level integration remains underexplored. This paper proposes a unified functional architecture for DTs in PV applications, encompassing real-time monitoring, signal processing, control synchronization, and AI-enabled forecasting. We systematically categorize the enabling technologies—including IoT platforms, edge–cloud orchestration, and cyber–physical system (CPS) integration—and analyze their roles across the DT lifecycle. Furthermore, case-driven evaluations illustrate practical implementation challenges, performance metrics, and deployment strategies. The proposed framework offers a scalable and interoperable blueprint to guide the development of intelligent DT infrastructures for next-generation solar energy systems.

Biomedical signals such as electroencephalogram (EEG), electrocardiogram (ECG), intracranial pressure (ICP), and photoplethysmogram (PPG) encode complex dynamical patterns that reflect the adaptive control of physiological systems. Complexity analysis—through entropy, compression, and causality metrics—has emerged as a critical tool for early diagnosis, risk prediction, and continuous monitoring in clinical and wearable settings. This review presents a clinically grounded synthesis of key complexity measures, including Sample Entropy (SampEn), Permutation Entropy (PE), Lempel–Ziv Complexity (LZC), and Effort-to-Compress (ETC), as well as causal inference techniques like Granger Causality, Transfer Entropy, and Compression–Complexity Causality (CCC). Applications across neurological and cardiovascular pathologies—such as epilepsy and sudden unexpected death in epilepsy (SUDEP)—are examined alongside signal-specific preprocessing, interpretability, and statistical validation strategies. We further evaluate the feasibility of deploying these measures in real-time on constrained hardware platforms—microcontrollers, FPGAs, and RISC–V-based SoCs—highlighting their suitability for embedded health systems and remote diagnostics. The review also explores synergistic integration with explainable machine learning, showing how complexity-informed features can enhance both performance and interpretability. By bridging signal complexity with hardware-aware deployment, ML transparency, and clinical translation, this work aims to guide the development of scalable, interpretable, and secure biomedical analytics for next-generation digital health systems.

Due to the increasing size and complexity of system-on-chips (SoCs), new threats and vulnerabilities are emerging, mainly related to flaws at the system level. Due to the lack of decisive security requirements and properties from the perspective of the SoC designer, the system-level verification process, whose violation may lead to exploiting a hardware vulnerability, is not studied comprehensively. To enable more comprehensive verification of system-level properties, this paper presents a framework known as HUnTer (Hardware Underath Trigger) for identifying sets of instructions (sequences) at the processor unit (PU) that reveal the underlying hardware vulnerabilities. HUnTer automates (i) threat modeling, (ii) threat-based formal verification, (iii) generating counterexamples, and (iv) generating snippet code to exploit the vulnerability. Furthermore, the HUnTer framework defines a unique security coverage metric ( HUnT_Coverage ) to measure the performance and effectiveness of vulnerability exploits. To demonstrate the high effectiveness of the proposed framework, we conduct a wide variety of case studies using the HUnTer framework on RISC-V-based open-source SoC architecture and attains the security coverage of 86% as an average for 11 benchmarks of the Trust-Hub database.