Elham Amini
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Previous Organizations / Institutes
The organizations / institutes from the scholar's other articles in the past ten years
Research Subjects
Elham Amini has a total of 59 co-authors. Here are the top co-authors by number of shared publications:
C. Boit
Department for Semiconductor Devices, Technical University Berlin, Berlin, Germany
4 shared publications- Jean-Pierre Seifert
Technische Universität Berlin, Berlin, Germany
4 shared publications A. Beyreuther
Department for Semiconductor Devices, Technical University Berlin, Berlin, Germany
3 shared publicationsN. Herfurth
Department for Semiconductor Devices, Technical University Berlin, Berlin, Germany
3 shared publicationsAli Rostami
Photonics and Nanocrystal Research Laboratory, Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz, Iran
2 shared publications- Ali Rostami
Photonics and Nanocrystal Research Lab. (PNRL), University of Tabriz, Tabriz, Iran
2 shared publications
Latest Publications
- Open Access
- 2 November 2026
- Published by Association for Computing Machinery (ACM)
- p. 215-225
What Happens Before the Hash? Layer-Aware Statistical Testing in a Live QKD Pipeline
- 2 November 2026
- Published by Association for Computing Machinery (ACM)
- p. 215-225
Open AccessWhat Happens Before the Hash? Layer-Aware Statistical Testing in a Live QKD Pipeline
- 24 July 2026
- Published by Springer Nature
- p. 397-425
Photons are Perfect, Protocols are Not: Cracking QKD BBM92 via the Internet
- 24 July 2026
- Published by Springer Nature
- p. 397-425
Photons are Perfect, Protocols are Not: Cracking QKD BBM92 via the Internet
- Open Access
- 16 March 2025
- Published by Association for Computing Machinery (ACM)
- p. 74-82
Photonic Side-Channel Analyzer: Enabling Security-Aware Physical Design Methodology
- 16 March 2025
- Published by Association for Computing Machinery (ACM)
- p. 74-82
Open AccessPhotonic Side-Channel Analyzer: Enabling Security-Aware Physical Design Methodology
- 25 April 2021
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1-12
Special Session: Physical Attacks through the Chip Backside: Threats, Challenges, and Opportunities
This paper reviews the evolution of a powerful class of physical attacks against integrated circuits (ICs), developed initially for performing failure analysis (FA) from the IC backside. Over the last two decades, several publications have demonstrated the effectiveness of these techniques in bypassing the IC protection schemes and extracting the stored assets inside secure ICs. In this work, we take a fresh look at such hardware attacks from three different perspectives. First, we will discuss the potential threat of the attacks against modern technologies and demystify a set of wrong beliefs about the attacks' complexity. Second, we review some technical challenges of such attacks from a law enforcement agency's perspective for unraveling crimes and preventing further crimes by criminals involved. Finally, we give an insight into the future development of FA tools and the opportunities for designing effective countermeasures against attacks through the chip backside.
- 25 April 2021
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1-12
Special Session: Physical Attacks through the Chip Backside: Threats, Challenges, and Opportunities
This paper reviews the evolution of a powerful class of physical attacks against integrated circuits (ICs), developed initially for performing failure analysis (FA) from the IC backside. Over the last two decades, several publications have demonstrated the effectiveness of these techniques in bypassing the IC protection schemes and extracting the stored assets inside secure ICs. In this work, we take a fresh look at such hardware attacks from three different perspectives. First, we will discuss the potential threat of the attacks against modern technologies and demystify a set of wrong beliefs about the attacks' complexity. Second, we review some technical challenges of such attacks from a law enforcement agency's perspective for unraveling crimes and preventing further crimes by criminals involved. Finally, we give an insight into the future development of FA tools and the opportunities for designing effective countermeasures against attacks through the chip backside.
- 1 March 2019
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1-9
New Access to Soft Breakdown Parameters of Low-k Dielectrics Through Localisation-Based Analysis
This paper provides a further understanding of soft breakdown (SBD) defects occurring in metal insulator metal (MIM) back end of line (BEOL) test structures with copper metallization and a low-k dielectric. Metal insulator semiconductor (MIS) test structures are utilised to take advantage of the infrared transparent backside of the silicon chip to directly access the low-k material. Transmission electron microscopy (TEM) images and scanning transmission electron microscope energy dispersive X-ray (STEM-EDX) analysis of localised SBD defects with a resistance of 250GΩ are shown. The temperature within the defective area during the SBD is estimated to be >802°C. A numerical solver program is used to simulate the thermal conditions. An energy density of at least 2E14 pW/μ m 3 is required to generate the presented defect morphology. Similarities between photon emission measurements (PEM) on MIM and MIS test structures allow transferring findings made on MIS structures to MIM structures. Spectral photon emission measurements (SPEM) are presented as a means to monitor the low-k degradation.
- 1 March 2019
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1-9
New Access to Soft Breakdown Parameters of Low-k Dielectrics Through Localisation-Based Analysis
This paper provides a further understanding of soft breakdown (SBD) defects occurring in metal insulator metal (MIM) back end of line (BEOL) test structures with copper metallization and a low-k dielectric. Metal insulator semiconductor (MIS) test structures are utilised to take advantage of the infrared transparent backside of the silicon chip to directly access the low-k material. Transmission electron microscopy (TEM) images and scanning transmission electron microscope energy dispersive X-ray (STEM-EDX) analysis of localised SBD defects with a resistance of 250GΩ are shown. The temperature within the defective area during the SBD is estimated to be >802°C. A numerical solver program is used to simulate the thermal conditions. An energy density of at least 2E14 pW/μ m 3 is required to generate the presented defect morphology. Similarities between photon emission measurements (PEM) on MIM and MIS test structures allow transferring findings made on MIS structures to MIM structures. Spectral photon emission measurements (SPEM) are presented as a means to monitor the low-k degradation.
- 17 October 2018
- Published by Springer Nature in Journal of Hardware and Systems Security
- Vol. 2 (4) , 345-352
Assessment of a Chip Backside Protection
- 17 October 2018
- Published by Springer Nature in Journal of Hardware and Systems Security
- Vol. 2 (4) , 345-352
Assessment of a Chip Backside Protection
- 30 September 2018
- Published by Elsevier in Microelectronics Reliability
- Vol. 88-90, 273-276
Photon emission as a characterization tool for bipolar parasitics in FinFET technology
- 30 September 2018
- Published by Elsevier in Microelectronics Reliability
- Vol. 88-90, 273-276
Photon emission as a characterization tool for bipolar parasitics in FinFET technology
- 1 September 2018
- Published by Elsevier in Microelectronics Reliability
- Vol. 88-90, 22-25
IC security and quality improvement by protection of chip backside against hardware attacks
- 1 September 2018
- Published by Elsevier in Microelectronics Reliability
- Vol. 88-90, 22-25
IC security and quality improvement by protection of chip backside against hardware attacks
- 1 November 2017
- Published by ASM International
- Vol. 81504, 279-284
Backside Protection Structure for Security Sensitive ICs
Modern integrated circuits (ICs) are in permanent risk of hardware attacks on sensitive data. But, proper and affordable protection of the IC backside against Focused Ion Beam (FIB) and optical fault injection attacks is missing. In this work, we investigate a patent [1] that uses p-n junctions as light emitters (forward bias) and detectors. We improved the backside detection mechanism presented in the patent by developing a test structure and adding an optically active layer on the backside as protective element to detect an attacked backside with electrical signals in the IC. The angle dependent reflection provided by the layer acts as the protective function. We demonstrate how the light emission and detection concept is quantitatively working and how the active layer produces a backside layer integrity related signal in the IC which can act as attack indicator. We also show that, due to the weak light emission intensity of silicon and the high excitation current, influences such as multi-angle reflection and stray current are reducing the angle-dependent effect on the signal and have to be taken into account in practical use.
- 1 November 2017
- Published by ASM International
- Vol. 81504, 279-284
Backside Protection Structure for Security Sensitive ICs
Modern integrated circuits (ICs) are in permanent risk of hardware attacks on sensitive data. But, proper and affordable protection of the IC backside against Focused Ion Beam (FIB) and optical fault injection attacks is missing. In this work, we investigate a patent [1] that uses p-n junctions as light emitters (forward bias) and detectors. We improved the backside detection mechanism presented in the patent by developing a test structure and adding an optically active layer on the backside as protective element to detect an attacked backside with electrical signals in the IC. The angle dependent reflection provided by the layer acts as the protective function. We demonstrate how the light emission and detection concept is quantitatively working and how the active layer produces a backside layer integrity related signal in the IC which can act as attack indicator. We also show that, due to the weak light emission intensity of silicon and the high excitation current, influences such as multi-angle reflection and stray current are reducing the angle-dependent effect on the signal and have to be taken into account in practical use.
- 12 September 2016
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 365-369
From IC debug to hardware security risk: The power of backside access and optical interaction
IC debug and diagnosis techniques like photon emission and FIB circuit edit are well established as powerful ways to attack secret codes in security ICs through chip frontside. But protective additions like interconnect meshes serve as countermeasures. This work shows examples how the risk assessment of contactless fault isolation (CFI) techniques through chip backside has indicated a drastic increase of vulnerability. Acclaimed unclonable functions and keys have been successfully challenged. There is no low-cost electronic backside protection concept available like the frontside meshes, because alignment and contact of backside structures to active IC layers cannot be handled without expensive through-silicon-via (TSV) technologies. But optical interaction can also be used to create backside protection concepts: Such concepts based on electro-optical properties are presented and proven to be operational.
- 12 September 2016
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 365-369
From IC debug to hardware security risk: The power of backside access and optical interaction
IC debug and diagnosis techniques like photon emission and FIB circuit edit are well established as powerful ways to attack secret codes in security ICs through chip frontside. But protective additions like interconnect meshes serve as countermeasures. This work shows examples how the risk assessment of contactless fault isolation (CFI) techniques through chip backside has indicated a drastic increase of vulnerability. Acclaimed unclonable functions and keys have been successfully challenged. There is no low-cost electronic backside protection concept available like the frontside meshes, because alignment and contact of backside structures to active IC layers cannot be handled without expensive through-silicon-via (TSV) technologies. But optical interaction can also be used to create backside protection concepts: Such concepts based on electro-optical properties are presented and proven to be operational.